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Timing

Sachin Sapatnekar

Published by Springer
ISBN 10: 1402076711 / ISBN 13: 9781402076718
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Title: Timing

Publisher: Springer

Binding: Hardcover

Book Condition: New

Book Type: Hardcover

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Hardcover. 294 pages. Dimensions: 9.5in. x 6.2in. x 0.9in.Statistical timing analysis is an area of growing importance in nanometer te- nologies as the uncertainties associated with process and environmental var- tions increase and this chapter has captured some of the major efforts in this area. This remains a very active field of research and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book the reader is referred to LNPS00 HN01 JH01 ABZ03a for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7. 1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7. 1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I M inputs and O M outputs. This item ships from multiple locations. Your book may arrive from Roseburg,OR, La Vergne,TN. Bookseller Inventory # 9781402076718

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Synopsis: Statistical timing analysis is an area of growing importance in nanometer te- nologies? as the uncertainties associated with process and environmental var- tions increase? and this chapter has captured some of the major efforts in this area. This remains a very active field of research? and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits? a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book? the reader is referred to [LNPS00? HN01? JH01? ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs.

Product Description: With the advent of nanometer technologies, circuit performance constraints are becoming ever more stringent. In this context, automated timing analysis and optimization becomes imperative for the design of high-performance circuits that must satisfy a demanding set of constraints. Timing overviews the state of the art in timing analysis and optimization, and is intended to serve as a compendium that can provide an introduction to the uninitiated reader, as a ready reference for a practitioner, or as a source for the accomplished researcher. A comprehensive overview of the basics of timing analysis is provided, and this is augmented with techniques that incorporate physical effects arising in deep submicron and nanometer technologies. The book provides an in-depth treatment of the analysis of interconnect systems, static timing analysis for combinational circuits, timing analysis for sequential circuits, and timing optimization techniques at the transistor and layout levels. The intended audience includes CAD tool developers, graduate students, research professionals, and the merely curious.

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