Designers developing the low voltage, low power chips that enable small, portable devices, face a very particular set of challenges. This monograph details cutting-edge design techniques for the low power circuitry required by the many new miniaturized business and consumer products driving the electronics market.
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HIGH-POWER DESIGN FOR LOW-POWER CHIPS
Detailing the latest techniques in low-voltage VLSI design, Low-Voltage, Low-Power VLSI Subsystems is a focused tutorial providing immediate access to state-of-the-art, proven design techniques in CMOS, BiCMOS, and other in-demand applications. In this unique resource, Professors Yeo and Roy offer electronic and IC designers as well as students:
Kiat-Seng Yeo, Ph.D., is a recognized expert in CMOS technology and IC design. Sub-Dean and Associate Professor of Electrical and Electronic Engineering at Nangyang Technological University in Singapore, he has published over 130 papers in his areas of expertise.
Kaushik Roy, Ph.D., is Professor of Electrical Engineering at Purdue University and a widely known authority on circuit design. Author of more than 200 papers in refereed journals and conferences, he serves on the editorial boards of IEEE Design and Test, IEEE Transactions on Circuits and Systems, and IEEE Transactions on VLSI Systems.
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