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64-Bit Dynamic Feedthrough Logic Adder

Sachin Vishwakarma

ISBN 10: 3659182745 / ISBN 13: 9783659182747
Published by LAP Lambert Academic Publishing
New Condition: New Paperback
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Paperback. 72 pages. Dimensions: 8.7in. x 5.9in. x 0.2in.CMOS is an attractive technology for the realization of Very large Scale Integration (VLSI) system. Over past decade, CMOS technology has played an increasingly important role in the global integrated circuit design. However conventional static CMOS design techniques suffer from the drawback of higher penalty on silicon area, less density packed , low speed and high power dissipation. In these cases, it is desirable to implement smaller and faster gates. The increasing demand for low power very large scale integration (VLSI) can be addressed at different design levels, such as the architecture, circuit, and layout level. Addition is the most commonly used arithmetic operation in microprocessor and DSPs, and it is often one of the speed-limiting-element. Hence optimization of the adder both in terms of speed andor power consumption should be pursued. During the design of an adder we have to make two choices in regard to different design abstraction levels. One is the responsible for the adders architecture implemented with the one-bit full adder as a building block . The other defines the specific design style at transistor level to implement the one-bit full adder. This item ships from multiple locations. Your book may arrive from Roseburg,OR, La Vergne,TN. Bookseller Inventory # 9783659182747

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Bibliographic Details

Title: 64-Bit Dynamic Feedthrough Logic Adder

Publisher: LAP Lambert Academic Publishing

Binding: Paperback

Book Condition:New

Book Type: Paperback

About this title

Synopsis:

CMOS is an attractive technology for the realization of Very large Scale Integration (VLSI) system. Over past decade, CMOS technology has played an increasingly important role in the global integrated circuit design. However conventional static CMOS design techniques suffer from the drawback of higher penalty on silicon area, less density packed , low speed and high power dissipation. In these cases, it is desirable to implement smaller and faster gates.The increasing demand for low power very large scale integration (VLSI) can be addressed at different design levels,such as the architecture,circuit, and layout level. Addition is the most commonly used arithmetic operation in microprocessor and DSPs, and it is often one of the speed-limiting-element. Hence optimization of the adder both in terms of speed and/or power consumption should be pursued. During the design of an adder we have to make two choices in regard to different design abstraction levels. One is the responsible for the adder?s architecture implemented with the one-bit full adder as a building block .The other defines the specific design style at transistor level to implement the one-bit full adder.

About the Author:

Currently Working as an Assistant Professor in SRITS Datia (M.P.) India in ECE Department. I obtain my MSc.(Electronics & communication) from Bundelkhand University Campus Jhansi (U.P.) India in 2007 and Received my M.Tech. Degree from Centre For Development of Advanced Computing Noida Affiliated To GGSIPU Delhi India in VLSI Technology in 2010.

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