Starter's Guide to Verilog 2001

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9780131415560: Starter's Guide to Verilog 2001

Introducing the Verilog HDL in a brief format, this book presents a selected set of the changes the popular hardware underwent in its first revision—emerging as IEEE Std 1364-2001 or Verilog-2001. It addresses the main features that support the design of combinational and sequential logic, and emphasizes synthesizable models, with a limited discussion of the theoretical framework for synthesis. Chapter topics cover an Introduction to Digital Design Methodology; Basic Concepts: Primitives, Data Types, and Operators in Verilog; Modeling Structure with Verilog; Modeling Behavior with Verilog; and Modeling Finite-State Mechanics and Datapath Controllers with Verilog. For designers with no backgrounds in HDLs, and designers familiar with Verilog 1995 and interested in the new features of Verilog 2001.

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Book Description Pearson Education (US), United States, 2003. Hardback. Book Condition: New. 2001 ed.. Language: English . Brand New Book. For undergraduate courses in Advanced Digital Logic and Advanced Digital Design in departments of electrical engineering, computer engineering, and computer science. Introducing the Verilog HDL in a brief format, this text presents a selected set of the changes the popular hardware underwent in its first revision-emerging as IEEE Std 1364-2001 or Verilog-2001. It addresses the main features that support the design of combinational and sequential logic, and emphasizes synthesizable models, with a limited discussion of the theoretical framework for synthesis. Bookseller Inventory # AAS9780131415560

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Book Description Pearson Education (US), United States, 2003. Hardback. Book Condition: New. 2001 ed.. Language: English . Brand New Book. For undergraduate courses in Advanced Digital Logic and Advanced Digital Design in departments of electrical engineering, computer engineering, and computer science. Introducing the Verilog HDL in a brief format, this text presents a selected set of the changes the popular hardware underwent in its first revision-emerging as IEEE Std 1364-2001 or Verilog-2001. It addresses the main features that support the design of combinational and sequential logic, and emphasizes synthesizable models, with a limited discussion of the theoretical framework for synthesis. Bookseller Inventory # AAS9780131415560

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