A Vhdl Primer - Hardcover

Bhasker, Jayaram

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Hardcover

ISBN 10: 013952987X ISBN 13: 9780139529870

Publisher: Prentice Hall, 1992

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An introduction to VHDL, clarifying the language by presenting a subset of VHDL so readers can quickly start writing models. It presents the most common usage instead of describing the complete syntax of language constructs. Describing the basic elements of the language, the author includes a quick tutorial to demonstrate the primary modelling features. It also provides illustrative examples that explain the different formulations of the language constructs and their semantics.

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From the Publisher:

VHDL is an IEEE standard as well as an ANSI standard language for describing digital designs--but it is a large and verbose language with many complex constructs that have complex semantic meaning, and is difficult to understand initially. (VDHL is often quoted as an acronym for Very Hard Description Language!) This primer--updated to include the new standard just released by the IEEE (IEEE Std 1076-1993)--uses a subset of the language to introduce VDHL to readers at the beginner's level. It explains the complex constructs of the language using an example-based approach. Covers topics such as basic language elements, behavioral modeling, dataflow modeling, structural modeling, generics and configurations, subprograms and overloading, packages and libraries, advanced features, model simulation, and hardware modeling examples. For both hardware and software designers interested in learning VHDL.

From the Back Cover:

The power of VHDL-without the complexity! Want to leverage VHDL's remarkable power without bogging down in its notorious complexity? Get A VHDL Primer, Third Edition. This up-to-the-minute introduction to VHDL focuses on the features you need to get results-with extensive practical examples so you can start writing VHDL models immediately. Written by Jayaram Bhasker, one of the world's leading VHDL course developers, this best-selling guide has been completely updated to reflect the popular IEEE STD_LOGIC_1164 package. With Bhasker's help, you'll master all these key VHDL techniques:

Behavioral, dataflow and structural modeling.
Generics and configurations.
Subprograms and overloading.
Packages and libraries.
Model simulation.
Advanced features: Entity statements, generate statements, aliases, guarded signals, attributes, aggregate targets, and more.

The book's extensive hardware modeling coverage includes modeling of regular structures, delays, conditional operations, state machines, Moore and Mealy FSMs, clock dividers and much more. You'll find new coverage of text I/O and test benches, as well as complete listings of the IEEE TD_LOGIC_1164 package. J. Bhasker has helped tens of thousands of professionals master VHDL. With A VHDL Primer, Third Edition, it's your turn to succeed.

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