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This handbook seeks to provide an in-depth and practical understanding of the digital clock technologies used in building today's telecommunications networks. Covering critical details on the PLL (phase-locked loop) technique for clock synchronization and generation, and the DDS (direct digital synthesizer) technique for clock generation, the work is designed to help the reader achieve synchronization in high-speed networks and frequency stabilization in portable equipment. Discussing both wired and wireless networks, the volume looks at the combination of circuits and systems to give you a more thorough understanding of important design requirements.
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Masami Kihara is a senior research engineer supervisor at NTT Microsystem Integration Laboratories. He has extensive practical experience designing frequency/time systems used in the commercial network of Nippon Telegraph and Telephone Corporation. He holds a B.S. in electrical engineering and Ph.D. in engineering from Nihon University.
Sadayasu Ono is a research fellow at NTT Network Innovation Laboratories, and a professor at Faculty of Environmental Information, Keio University. He received his Ph.D. in electrical engineering from Keio University.
Pekka Eskelinen is a professor at the Helsinki University of Technology, Radio Laboratory, IDC, where he received his Ph.D. in electrical engineering. He is also an associate editor for the IEEE Aerospace and Electronic Systems Society.
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Book Description Artech House 2002, 2002. Condition: New. New hardback. Fine and unread. Seller Inventory # A50133
Book Description Artech House, 2002. Hardcover. Condition: New. Never used!. Seller Inventory # P111580535062
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Book Description Artech House, 2002. Condition: New. book. Seller Inventory # M1580535062
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