FPGA Based Self-test Systems: Design and development of reconfigurable and automated test systems to characterize high-speed interfaces

 
9783659273469: FPGA Based Self-test Systems: Design and development of reconfigurable and automated test systems to characterize high-speed interfaces
View all copies of this ISBN edition:
 
 

With I/O speeds increasing rapidly, there is a need to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. Traditionally, Bit Error Rate (BER) is evaluated using software simulations and stand-alone BER test products, which are either time-consuming or expensive. In this book, I demonstrate the design and implementation of a self-contained FPGA-based systems that can be used to test these interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gb/s per channel. This includes the design of high-speed random pattern generator designs in Verilog and C-code for the integrated Power-PC processor to handle control of the user interface. The book also includes schematics of the current system and board design ideas for the readers to design their own systems.

"synopsis" may belong to another edition of this title.

About the Author:

Manav Shah is a hardware engineer with over 10 years of experience in designing ASIC and FGPA-based systems. He has worked with ISRO(Indian Space Research Organization), IBM Corp, and is currently employed as an ASIC designer at Qualcomm Inc. He holds an MS degree in Electrical Engineering and is currently pursuing an MS in Wireless health devices

"About this title" may belong to another edition of this title.

Buy New View Book
List Price: US$ 63.00
US$ 53.30

Convert currency

Shipping: US$ 3.43
From Germany to U.S.A.

Destination, rates & speeds

Add to Basket

Top Search Results from the AbeBooks Marketplace

1.

Shah, Manav
ISBN 10: 3659273465 ISBN 13: 9783659273469
New Quantity Available: 1
Seller:
Rating
[?]

Book Description Condition: New. Publisher/Verlag: LAP Lambert Academic Publishing | Design and development of reconfigurable and automated test systems to characterize high-speed interfaces | With I/O speeds increasing rapidly, there is a need to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. Traditionally, Bit Error Rate (BER) is evaluated using software simulations and stand-alone BER test products, which are either time-consuming or expensive. In this book, I demonstrate the design and implementation of a self-contained FPGA-based systems that can be used to test these interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gb/s per channel. This includes the design of high-speed random pattern generator designs in Verilog and C-code for the integrated Power-PC processor to handle control of the user interface. The book also includes schematics of the current system and board design ideas for the readers to design their own systems. | Format: Paperback | Language/Sprache: english | 116 pp. Seller Inventory # K9783659273469

More information about this seller | Contact this seller

Buy New
US$ 53.30
Convert currency

Add to Basket

Shipping: US$ 3.43
From Germany to U.S.A.
Destination, rates & speeds

2.

Shah Manav (author)
Published by LAP Lambert Academic Publishing 2012-11-10 (2012)
ISBN 10: 3659273465 ISBN 13: 9783659273469
New paperback Quantity Available: > 20
Seller:
Blackwell's
(Oxford, OX, United Kingdom)
Rating
[?]

Book Description LAP Lambert Academic Publishing 2012-11-10, 2012. paperback. Condition: New. Seller Inventory # 9783659273469

More information about this seller | Contact this seller

Buy New
US$ 47.12
Convert currency

Add to Basket

Shipping: US$ 9.72
From United Kingdom to U.S.A.
Destination, rates & speeds

3.

Shah Manav
Published by LAP Lambert Academic Publishing (2016)
ISBN 10: 3659273465 ISBN 13: 9783659273469
New Paperback Quantity Available: 1
Print on Demand
Seller:
Ria Christie Collections
(Uxbridge, United Kingdom)
Rating
[?]

Book Description LAP Lambert Academic Publishing, 2016. Paperback. Condition: New. PRINT ON DEMAND Book; New; Publication Year 2016; Not Signed; Fast Shipping from the UK. No. book. Seller Inventory # ria9783659273469_lsuk

More information about this seller | Contact this seller

Buy New
US$ 55.09
Convert currency

Add to Basket

Shipping: US$ 5.02
From United Kingdom to U.S.A.
Destination, rates & speeds

4.

Shah Manav
Published by LAP Lambert Academic Publishing (2012)
ISBN 10: 3659273465 ISBN 13: 9783659273469
New Quantity Available: > 20
Print on Demand
Seller:
Books2Anywhere
(Fairford, GLOS, United Kingdom)
Rating
[?]

Book Description LAP Lambert Academic Publishing, 2012. PAP. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Seller Inventory # LQ-9783659273469

More information about this seller | Contact this seller

Buy New
US$ 49.68
Convert currency

Add to Basket

Shipping: US$ 11.67
From United Kingdom to U.S.A.
Destination, rates & speeds

5.

Shah Manav
Published by LAP Lambert Academic Publishing (2012)
ISBN 10: 3659273465 ISBN 13: 9783659273469
New Quantity Available: > 20
Print on Demand
Seller:
Pbshop
(Wood Dale, IL, U.S.A.)
Rating
[?]

Book Description LAP Lambert Academic Publishing, 2012. PAP. Condition: New. New Book. Shipped from US within 10 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Seller Inventory # IQ-9783659273469

More information about this seller | Contact this seller

Buy New
US$ 58.49
Convert currency

Add to Basket

Shipping: US$ 3.99
Within U.S.A.
Destination, rates & speeds

6.

Manav Shah
Published by LAP Lambert Academic Publishing Nov 2012 (2012)
ISBN 10: 3659273465 ISBN 13: 9783659273469
New Taschenbuch Quantity Available: 1
Seller:
BuchWeltWeit Inh. Ludwig Meier e.K.
(Bergisch Gladbach, Germany)
Rating
[?]

Book Description LAP Lambert Academic Publishing Nov 2012, 2012. Taschenbuch. Condition: Neu. Neuware - With I/O speeds increasing rapidly, there is a need to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. Traditionally, Bit Error Rate (BER) is evaluated using software simulations and stand-alone BER test products, which are either time-consuming or expensive. In this book, I demonstrate the design and implementation of a self-contained FPGA-based systems that can be used to test these interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gb/s per channel. This includes the design of high-speed random pattern generator designs in Verilog and C-code for the integrated Power-PC processor to handle control of the user interface. The book also includes schematics of the current system and board design ideas for the readers to design their own systems. 116 pp. Englisch. Seller Inventory # 9783659273469

More information about this seller | Contact this seller

Buy New
US$ 57.86
Convert currency

Add to Basket

Shipping: US$ 19.64
From Germany to U.S.A.
Destination, rates & speeds

7.

Manav Shah
Published by LAP Lambert Academic Publishing Nov 2012 (2012)
ISBN 10: 3659273465 ISBN 13: 9783659273469
New Taschenbuch Quantity Available: 1
Seller:
Rheinberg-Buch
(Bergisch Gladbach, Germany)
Rating
[?]

Book Description LAP Lambert Academic Publishing Nov 2012, 2012. Taschenbuch. Condition: Neu. Neuware - With I/O speeds increasing rapidly, there is a need to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. Traditionally, Bit Error Rate (BER) is evaluated using software simulations and stand-alone BER test products, which are either time-consuming or expensive. In this book, I demonstrate the design and implementation of a self-contained FPGA-based systems that can be used to test these interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gb/s per channel. This includes the design of high-speed random pattern generator designs in Verilog and C-code for the integrated Power-PC processor to handle control of the user interface. The book also includes schematics of the current system and board design ideas for the readers to design their own systems. 116 pp. Englisch. Seller Inventory # 9783659273469

More information about this seller | Contact this seller

Buy New
US$ 57.86
Convert currency

Add to Basket

Shipping: US$ 19.64
From Germany to U.S.A.
Destination, rates & speeds

8.

Manav Shah
Published by LAP Lambert Academic Publishing
ISBN 10: 3659273465 ISBN 13: 9783659273469
New Paperback Quantity Available: > 20
Seller:
BuySomeBooks
(Las Vegas, NV, U.S.A.)
Rating
[?]

Book Description LAP Lambert Academic Publishing. Paperback. Condition: New. 116 pages. Dimensions: 8.7in. x 5.9in. x 0.3in.With IO speeds increasing rapidly, there is a need to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. Traditionally, Bit Error Rate (BER) is evaluated using software simulations and stand-alone BER test products, which are either time-consuming or expensive. In this book, I demonstrate the design and implementation of a self-contained FPGA-based systems that can be used to test these interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gbs per channel. This includes the design of high-speed random pattern generator designs in Verilog and C-code for the integrated Power-PC processor to handle control of the user interface. The book also includes schematics of the current system and board design ideas for the readers to design their own systems. This item ships from multiple locations. Your book may arrive from Roseburg,OR, La Vergne,TN. Paperback. Seller Inventory # 9783659273469

More information about this seller | Contact this seller

Buy New
US$ 85.45
Convert currency

Add to Basket

Shipping: FREE
Within U.S.A.
Destination, rates & speeds

9.

Manav Shah
Published by LAP LAMBERT Academic Publishing (2012)
ISBN 10: 3659273465 ISBN 13: 9783659273469
New Softcover Quantity Available: 1
Seller:
Irish Booksellers
(Portland, ME, U.S.A.)
Rating
[?]

Book Description LAP LAMBERT Academic Publishing, 2012. Condition: New. book. Seller Inventory # M3659273465

More information about this seller | Contact this seller

Buy New
US$ 83.72
Convert currency

Add to Basket

Shipping: US$ 3.27
Within U.S.A.
Destination, rates & speeds

10.

Shah Manav
Published by LAP Lambert Academic Publishing, United States (2012)
ISBN 10: 3659273465 ISBN 13: 9783659273469
New Paperback Quantity Available: 10
Seller:
The Book Depository EURO
(London, United Kingdom)
Rating
[?]

Book Description LAP Lambert Academic Publishing, United States, 2012. Paperback. Condition: New. Language: English. Brand new Book. With I/O speeds increasing rapidly, there is a need to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. Traditionally, Bit Error Rate (BER) is evaluated using software simulations and stand-alone BER test products, which are either time-consuming or expensive. In this book, I demonstrate the design and implementation of a self-contained FPGA-based systems that can be used to test these interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gb/s per channel. This includes the design of high-speed random pattern generator designs in Verilog and C-code for the integrated Power-PC processor to handle control of the user interface. The book also includes schematics of the current system and board design ideas for the readers to design their own systems. Seller Inventory # AAV9783659273469

More information about this seller | Contact this seller

Buy New
US$ 83.89
Convert currency

Add to Basket

Shipping: US$ 3.89
From United Kingdom to U.S.A.
Destination, rates & speeds

There are more copies of this book

View all search results for this book