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The Source/Drain Engineering of Nanoscale Germanium-based MOS Devices (Springer Theses) - Hardcover

 
9783662496817: The Source/Drain Engineering of Nanoscale Germanium-based MOS Devices (Springer Theses)

Synopsis

This book mainly focuses on reducing the high parasitic resistance in the source/drain of germanium nMOSFET. With  adopting of the Implantation After Germanide (IAG) technique, P and Sb co-implantation technique and Multiple Implantation and Multiple Annealing (MIMA) technique, the electron Schottky barrier height of NiGe/Ge contact is modulated to 0.1eV, the thermal stability of NiGe is improved to 600℃ and the contact resistivity of metal/n-Ge contact is drastically reduced to 3.8×10-7Ω•cm2, respectively. Besides, a reduced  source/drain parasitic resistance is demonstrated in the  fabricated Ge nMOSFET. Readers will find useful information about the source/drain engineering technique for high-performance CMOS devices at future technology node.

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About the Author

Dr. Li received his Bachelor degree of Science from Sichuan University in 2009, and Ph.D from Peking University in 2014

Prizes and awards:
2009-2014, Peking University
Leo KoGuan Scholarship, Chenming Hu Scholarship, Merit Student, Creative Talent Award.
2005-2009, Sichuan University
National Scholarship (twice), National Encouragement Scholarship, Xinyuan Scholarship (twice),
Comprehensive First-class Scholarship, Excellent Student Leader.

Publications:
 1. Zhiqiang Li, Xia An, Min Li, Quanxin Yun, Meng Lin, Ming Li, Xing Zhang, and Ru Huang, “Low Electron Schottky Barrier Height of NiGe/Ge Achieved by Ion-Implantation after Germanidation Technique,” IEEE Electron Device Lett.,vol. 33, no. 12, pp. 1687–1689, Dec. 2012.
2. Zhiqiang Li, Xia An, Min Li, Quanxin Yun, Meng Lin, Ming Li, Xing Zhang, and Ru Huang, “Morphology and Electrical Performance Improvement of NiGe/Ge Contact by P and Sb Co-implantation,” IEEE Electron Device Lett., vol. 34, no. 5, pp. 596–598, May. 2013.
3. Zhiqiang Li, Xia An, Quanxin Yun, Meng Lin, Min Li, Ming Li, Xing Zhang, and Ru Huang, “Low Specific Contact Resistivity to n-Ge and Well-Behaved Ge n⁺/p Diode Achieved by Multiple Implantation and Multiple Annealing Technique,” IEEE Electron Device Lett., vol. 34, no. 9, pp. 1097–1099, Sep. 2013.
4. Zhiqiang Li, Xia An, Quanxin Yun, Meng Lin, Xing Zhang and Ru Huang, “Tuning Schottky Barrier Height in Metal/n-Type Germanium by Inserting an Ultrathin Yttrium Oxide Film,” ECS Solid State Lett., Vol. 1, no. 4, pp. Q33-Q34, 2012.
5. Zhiqiang Li, Xia An, Min Li, Quanxin Yun, Meng Lin, Ming Li, Xing Zhang, and Ru Huang, “Study on Schottky Barrier Modulation of NiGe/Ge by Ion-implantation after Germanidation Technique,” The 11th ICSICT, Xi’an, 2012.
 

From the Back Cover

This book mainly focuses on reducing the high parasitic resistance in the source/drain of germanium nMOSFET. With  adopting of the Implantation After Germanide (IAG) technique, P and Sb co-implantation technique and Multiple Implantation and Multiple Annealing (MIMA) technique, the electron Schottky barrier height of NiGe/Ge contact is modulated to 0.1eV, the thermal stability of NiGe is improved to 600℃ and the contact resistivity of metal/n-Ge contact is drastically reduced to 3.8×10-7Ω•cm2, respectively. Besides, a reduced  source/drain parasitic resistance is demonstrated in the  fabricated Ge nMOSFET. Readers will find useful information about the source/drain engineering technique for high-performance CMOS devices at future technology node.

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  • PublisherSpringer
  • Publication date2016
  • ISBN 10 366249681X
  • ISBN 13 9783662496817
  • BindingHardcover
  • LanguageEnglish
  • Edition number1
  • Number of pages73

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Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book mainly focuses on reducing the high parasitic resistance in the source/drain of germanium nMOSFET. With adopting of the Implantation After Germanide (IAG) technique, P and Sb co-implantation technique and Multiple Implantation and Multiple Annealing (MIMA) technique, the electron Schottky barrier height of NiGe/Ge contact is modulated to 0.1eV, the thermal stability of NiGe is improved to 600 and the contact resistivity of metal/n-Ge contact is drastically reduced to 3.8×10-7 -cm2, respectively. Besides, a reduced source/drain parasitic resistance is demonstrated in the fabricated Ge nMOSFET. Readers will find useful information about the source/drain engineering technique for high-performance CMOS devices at future technology node. 80 pp. Englisch. Seller Inventory # 9783662496817

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Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book mainly focuses on reducing the high parasitic resistance in the source/drain of germanium nMOSFET. With adopting of the Implantation After Germanide (IAG) technique, P and Sb co-implantation technique and Multiple Implantation and Multiple Annealing (MIMA) technique, the electron Schottky barrier height of NiGe/Ge contact is modulated to 0.1eV, the thermal stability of NiGe is improved to 600 and the contact resistivity of metal/n-Ge contact is drastically reduced to 3.8×10-7 -cm2, respectively. Besides, a reduced source/drain parasitic resistance is demonstrated in the fabricated Ge nMOSFET. Readers will find useful information about the source/drain engineering technique for high-performance CMOS devices at future technology node. Seller Inventory # 9783662496817

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Buch. Condition: Neu. Neuware -This book mainly focuses on reducing the high parasitic resistance in the source/drain of germanium nMOSFET. With adopting of the Implantation After Germanide (IAG) technique, P and Sb co-implantation technique and Multiple Implantation and Multiple Annealing (MIMA) technique, the electron Schottky barrier height of NiGe/Ge contact is modulated to 0.1eV, the thermal stability of NiGe is improved to 600¿ and the contact resistivity of metal/n-Ge contact is drastically reduced to 3.8×10¿7¿¿cm2, respectively. Besides, a reduced source/drain parasitic resistance is demonstrated in the fabricated Ge nMOSFET. Readers will find useful information about the source/drain engineering technique for high-performance CMOS devices at future technology node.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 80 pp. Englisch. Seller Inventory # 9783662496817

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