Impact of Dynamic Voltage Scaling on Nano-Scale Circuit Optimization: 45-nm CMOS Technology

 
9783846584545: Impact of Dynamic Voltage Scaling on Nano-Scale Circuit Optimization: 45-nm CMOS Technology

Circuit designers perform optimization procedures targeting speed and power. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques applied to the circuit at a fixed voltage. DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during optimization at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under these circumstances. The following questions arise: 1) should we take DVS into account during optimization? 2) Does DVS impose any restrictions to design-time circuit optimizations? This is a case study of applying DVS to a circuit that has been optimized for speed and power, and aims at answering the previous two questions. We used a 45-nm CMOS design kit and flow for ISCAS’85 c432. Results showed that we should not optimize using Dual-VT at an arbitrary voltage but at the lowest in the DVS range, otherwise non-critical paths might become critical paths at run-time.

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About the Author:

Carlos Esquit received his B.Sc. degree in Electronics Engineering from del Valle de Guatemala University in 2003. He worked a few years for Siemens and then completed his M.Sc. degree in Computer Engineering at Texas A&M University in 2008. He is currently the Head of the Department of Electronics Engineering at del Valle de Guatemala University.

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Book Description Book Condition: New. Publisher/Verlag: LAP Lambert Academic Publishing | 45-nm CMOS Technology | Circuit designers perform optimization procedures targeting speed and power. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques applied to the circuit at a fixed voltage. DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during optimization at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under these circumstances. The following questions arise: 1) should we take DVS into account during optimization? 2) Does DVS impose any restrictions to design-time circuit optimizations? This is a case study of applying DVS to a circuit that has been optimized for speed and power, and aims at answering the previous two questions. We used a 45-nm CMOS design kit and flow for ISCAS 85 c432. Results showed that we should not optimize using Dual-VT at an arbitrary voltage but at the lowest in the DVS range, otherwise non-critical paths might become critical paths at run-time. | Format: Paperback | Language/Sprache: english | 68 pp. Bookseller Inventory # K9783846584545

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Book Description LAP Lambert Academic Publishing Feb 2012, 2012. Taschenbuch. Book Condition: Neu. Neuware - Circuit designers perform optimization procedures targeting speed and power. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques applied to the circuit at a fixed voltage. DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during optimization at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under these circumstances. The following questions arise: 1) should we take DVS into account during optimization 2) Does DVS impose any restrictions to design-time circuit optimizations This is a case study of applying DVS to a circuit that has been optimized for speed and power, and aims at answering the previous two questions. We used a 45-nm CMOS design kit and flow for ISCAS 85 c432. Results showed that we should not optimize using Dual-VT at an arbitrary voltage but at the lowest in the DVS range, otherwise non-critical paths might become critical paths at run-time. 68 pp. Englisch. Bookseller Inventory # 9783846584545

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Book Description LAP Lambert Academic Publishing Feb 2012, 2012. Taschenbuch. Book Condition: Neu. Neuware - Circuit designers perform optimization procedures targeting speed and power. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques applied to the circuit at a fixed voltage. DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during optimization at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under these circumstances. The following questions arise: 1) should we take DVS into account during optimization 2) Does DVS impose any restrictions to design-time circuit optimizations This is a case study of applying DVS to a circuit that has been optimized for speed and power, and aims at answering the previous two questions. We used a 45-nm CMOS design kit and flow for ISCAS 85 c432. Results showed that we should not optimize using Dual-VT at an arbitrary voltage but at the lowest in the DVS range, otherwise non-critical paths might become critical paths at run-time. 68 pp. Englisch. Bookseller Inventory # 9783846584545

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Book Description LAP Lambert Academic Publishing. Paperback. Book Condition: New. Paperback. 68 pages. Dimensions: 8.8in. x 5.9in. x 0.1in.Circuit designers perform optimization procedures targeting speed and power. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques applied to the circuit at a fixed voltage. DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during optimization at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under these circumstances. The following questions arise: 1) should we take DVS into account during optimization 2) Does DVS impose any restrictions to design-time circuit optimizations This is a case study of applying DVS to a circuit that has been optimized for speed and power, and aims at answering the previous two questions. We used a 45-nm CMOS design kit and flow for ISCAS85 c432. Results showed that we should not optimize using Dual-VT at an arbitrary voltage but at the lowest in the DVS range, otherwise non-critical paths might become critical paths at run-time. This item ships from multiple locations. Your book may arrive from Roseburg,OR, La Vergne,TN. Paperback. Bookseller Inventory # 9783846584545

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Book Description LAP Lambert Academic Publishing, Germany, 2012. Paperback. Book Condition: New. Aufl.. Language: English . Brand New Book. Circuit designers perform optimization procedures targeting speed and power. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques applied to the circuit at a fixed voltage. DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during optimization at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under these circumstances. The following questions arise: 1) should we take DVS into account during optimization? 2) Does DVS impose any restrictions to design-time circuit optimizations? This is a case study of applying DVS to a circuit that has been optimized for speed and power, and aims at answering the previous two questions. We used a 45-nm CMOS design kit and flow for ISCAS 85 c432. Results showed that we should not optimize using Dual-VT at an arbitrary voltage but at the lowest in the DVS range, otherwise non-critical paths might become critical paths at run-time. Bookseller Inventory # KNV9783846584545

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