ISBN 13: 9789350381991


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Introduction Overview of VLSI design methodology, VLSI design flow, Design hierarchy, Concept of regularity, Modularity and locality, VLSI design style, Design quality, Package technology, Computer aided design technology. Fabrication of MOSFET Introduction, Fabrication process flow : Basic steps, C-MOS n-well process, Layout design rules, Full custom mask layout design. MOS Transistor The Metal Oxide Semiconductor (MOS) structure, The MOS system under external bias, Structure and operation of MOS transistor, MOSFET current-voltage characteristics, MOSFET scaling and small-geometry effects, MOSFET capacitances. MOS Inverters : Static Characteristics Introduction, Resistive load inverter, Inverter with n-type MOSFET load (Enhancement and depletion type MOSFET load), CMOS inverter. MOS Inverters : Switching Characteristics and Interconnect Effects Introduction, Delay-time definitions, Calculation of delay times, Inverter design with delay constraints, Estimation of interconnect parasitic, Calculation of interconnect delay, Switching power dissipation of CMOS inverters. Combinational MOS Logic Circuits Introduction, MOS logic circuits with depletion nMOS loads, CMOS logic circuits, Complex logic circuits, CMOS transmission gates (TGs). Sequential MOS Logic Circuits Introduction, Behaviour of bistable elements, The SR latch circuit, Clocked latch and flip-flop circuit, CMOS D-latch and edge-triggered flip-flop. Dynamic Logic Circuits Introduction, Basic principles of pass transistor circuits, Voltage bootstrapping, Synchronous dynamic circuit techniques, CMOS dynamic circuit techniques, High-performance dynamic CMOS circuits. Chip I/P and O/P Circuits On chip clock generation and distribution, Latch-up and its prevention. Design for Testability Introduction, Fault types and models, Controllability and observability, Ad-Hoc testable design techniques, Scan-based techniques, Built-In Self Test (BIST) techniques, Current monitoring IDDQ test. Introduction to Programmable Logic Devices FPGA and CPLD.

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