Design and Modeling for 3DICs and Interposers (Wspc Series in Advanced Integration and Packaging)

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9789814508599: Design and Modeling for 3DICs and Interposers (Wspc Series in Advanced Integration and Packaging)

3D Integration is being touted as the next semiconductor revolution. This book provides a comprehensive coverage on the design and modeling aspects of 3D integration, in particularly, focus on its electrical behavior. Looking from the perspective the Silicon Via (TSV) and Glass Via (TGV) technology, the book introduces 3DICs and Interposers as a technology, and presents its application in numerical modeling, signal integrity, power integrity and thermal integrity. The authors underscored the potential of this technology in design exchange formats and power distribution.

Readership: Graduate students, academics, researchers in electrical and electronics engineering, computer engineering, semiconductors and packaging.

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Madhavan Swaminathan is the John Pippin Chair in Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Interconnect and Packaging Center, Georgia Tech, USA and the Founder and CTO of E-System Design, a company focusing on the development of CAD tools for achieving signal and power integrity in integrated 3D micro and nano-systems. He is also the co-founder of Jacket Micro Devices, a company that specialized in integrated RF modules and substrates for wireless applications that was acquired by AVX Corporation. He formerly held the position of Joseph M. Pettit Professor in Electronics in ECE and Deputy Director of the NSF Microsystems Packaging Center at Georgia Tech. Prior to joining Georgia Tech, he was with IBM working on packaging for supercomputers. He is the author of more than 400 technical articles, holds 27 patents, is the author of 3 book chapters, primary author and co-editor of 3 books -- "Power Integrity Modeling and Design for Semiconductors and Systems", Prentice Hall, Nov 2007, "Introduction to System on Package", McGraw Hill, Mar. 2008 and "Design and Modeling for 3D ICs and Interposers", WSPC, Sep. 2013 in the field of packaging. He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE EMC society. Thirty-five Ph.D. and sixteen M.S. students in Electrical Engineering have graduated under his supervision. He received his B.E. degree in Electronics and Communication from Regional Engineering College, Tiruchirapalli, India (now NITT) in 1985 and M.S. and Ph.D. degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.

Ki Jin Han received the B.S. and M.S. degrees in electrical engineering from Seoul National University in 1998 and 2000, respectively, and the Ph.D. degree in electrical and computer engineering from Georgia Tech in 2009. From 2000 to 2005, he was with the System R&D Laboratory, LG Precision, Korea, where he was involved in the development of wireless transceiver and antenna system for airborne and naval radars. From 2006 to 2009, he was with Mixed Signal Design Group in Georgia Tech as a graduate research assistant. After graduation from Georgia Tech, Dr. Han was with the IBM T. J. Watson Research Center as a postdoctoral researcher. From 2011, he is with the School of ECE, Ulsan National Institute of Science and Technology (UNIST), Korea, as an assistant professor. In UNIST, Dr. Han is collaborating with E-System Design for the development of a 3-D integration design tool. Dr. Han was the recipient of the Samsung Scholarship for graduate study in 2005. He has been a reviewer of journals including IEEE Transactions on Components, Packaging and Manufacturing Technology. Throughout his research career, Dr. Han has been interested in simulation, modeling, and design of various electromagnetic applications, covering microwave circuits, antennas, signal/power integrity for high-speed digital design, and the electromagnetic modeling of electronic packaging and interconnections.

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