Architecture Support for Intrusion Detection systems

Govind Sreekar Shenoy

ISBN 10: 3659612774 / ISBN 13: 9783659612770

Published by LAP LAMBERT Academic Publishing Okt 2014, 2014

About this Item

Neuware -System security is a prerequisite for efficient day-to-day transactions. As a consequence, Intrusion Detection Systems (IDS) are commonly used to provide an effective security ring to systems in a network. An IDS operates by inspecting packets flowing in the network for malicious content. To do so, an IDS like Snort[49] compares bytes in a packet with a database of prior reported attacks. This functionality can also be viewed as string matching of the packet bytes with the attack string database. In this thesis we explore hardware and software techniques to accelerate string matching in an IDS. We propose mechanisms/hueristics that can be deployed either in a custom ASIC or a network processor and/or a commodity CPU. Our performance results indicate clear benefits in using our proposed scheme over the state-of-the-art.Books on Demand GmbH, Überseering 33, 22297 Hamburg 160 pp. Englisch.

Seller Inventory # 9783659612770

Bibliographic Details

• Title: Architecture Support for Intrusion Detection systems
• Publisher: LAP LAMBERT Academic Publishing Okt 2014
• Publication Date: 2014
• Language: English
• ISBN 10: 3659612774
• ISBN 13: 9783659612770
• Binding: Taschenbuch
• Condition: Neu

About this title

Synopsis

System security is a prerequisite for efficient day-to-day transactions. As a consequence, Intrusion Detection Systems (IDS) are commonly used to provide an effective security ring to systems in a network. An IDS operates by inspecting packets flowing in the network for malicious content. To do so, an IDS like Snort[49] compares bytes in a packet with a database of prior reported attacks. This functionality can also be viewed as string matching of the packet bytes with the attack string database. In this thesis we explore hardware and software techniques to accelerate string matching in an IDS. We propose mechanisms/hueristics that can be deployed either in a custom ASIC or a network processor and/or a commodity CPU. Our performance results indicate clear benefits in using our proposed scheme over the state-of-the-art.

About the Author

Govind currently is a post-doctoral research fellow at the University of Edinburgh. Govind completed his Doctorate from Universitat Politecnica De Catalunya, Barcelona in 2012. He completed his Master of Science in Engineering from the Indian Institute of Science, Bangalore. He also completed his Bachelors from MNIT, Jaipur.