Chip design CMOS analog integrated circuit layout design and verification: based on Cadence IC 6.1.7 version 2(Chinese Edition)

CHEN CHENG YING . CHEN LI MING . JIANG JIAN HUA . WANG XING HUA

Condition: New Soft cover

Sold by liu xing, Nanjing, JS, China

AbeBooks Seller since April 7, 2009

Seller rating 5 out of 5 stars 5-star rating, Learn more about seller ratings

View this seller's items


New - Soft cover

Condition: New

Price: US$ 178.58 Convert Currency
US$ 18.00 shipping from China to U.S.A. Destination, rates & speeds

Quantity: 3 available

Add to basket