Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development on customizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems.

About the Author

Yu-Ting Chen is a Ph.D. candidate in the Computer Science Department at the University of California, Los Angeles. He received a B.S. degree in computer science, a B.A. degree in economics, and an M.S. degree in computer science from National Tsing Hua University, HsinTsu, Taiwan, R.O.C., in 2005 and 2007, respectively. He worked at TSMC as a summer intern in 2005 and at Intel Labs as a summer intern in 2013. His research interests include computer architecture, cluster computing, and bioinformatics in DNA sequencing technologies.

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