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Design Through Verilog HDL

B. Bala Tripura Sundari,T.R. Padmanabhan

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ISBN 10: 8126519312 / ISBN 13: 9788126519316
Published by Wiley India Pvt. Ltd., 2008
New Condition: New Soft cover
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If you aspire to master Verilog language and become a competent EDA professional, this book is for you. It fills the need for an elaborate construct in Verilog, and clarifies their implications, illustrating their need and utility. This is especially true fo the latest IEEE Standard 1364 for Verilog. Contents:- Preface Acknowledgements ? Introduction to VLSI Design ? Introduction to Verilog ? Language Constructs and Conventions in Verilog ? Gate Level Modeling - 1 ? Gate Level Modeling - 2 ? Modeling at Data Flow Level ? Behavioral Modeling - 1 ? Behavioral Modeling II ? Functions, Tasks, and User-Defined Primitives ? Switch Level Modeling 305 ? System Tasks, Functions, and Compiler Directives 339 ? Queues, PLAS, and FSMS Appendix A (Keywords and Their Significance) Appendix B (Truth Tables of Gates and Switches) References Index Printed Pages: 472. Bookseller Inventory # 10407

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Bibliographic Details

Title: Design Through Verilog HDL

Publisher: Wiley India Pvt. Ltd.

Publication Date: 2008

Binding: Softcover

Book Condition:New

About this title

Synopsis:

If you aspire to master verilog language and become a competent eda professional, this book is for you. It fills the need for an elaborate construct in verilog, and clarifies their implications, illustrating their need and utility. This is especially true fo the latest ieee standard 1364 for verilog. · introduction to vlsi design · introduction to verilog · language constructs and conventions in verilog · gate level modeling - 1 · gate level modeling - 2 · modeling at data flow level · behavioral modeling - 1 · behavioral modeling ii · functions, tasks, and user-defined primitives · switch level modeling 305 · system tasks, functions, and compiler directives 339 · queues, plas, and fsms

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