An Efficient Implementation of High-Speed JPEG2000 Encoder/Decoder : ALGORITHMS, SPECIFICATIONS, DESIGN SPACE EXPLORATION

Michael Yaw Appiah

ISBN 10: 3838334760 / ISBN 13: 9783838334769

Published by LAP LAMBERT Academic Publishing, 2010

About this Item

nach der Bestellung gedruckt Neuware - Printed after ordering - This book presents a complete and up-to-date description of an efficient FPGA implementation of high-speed JPEG2000 using formal design methodologies namely SpecC and A3, in a systematic and clear manner. JPEG2000 proposes a large set of advanced features for today's internet and multimedia applications. At the heart of JPEG2000 are two complex DSP algorithms: Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optmized Truncation (EBCOT). Both algorithms are complex, compute intensive and very difficult to optimize in software implementation for real-time imaging and multimedia applications. A hardware implementation brings a solution to this complexity for real-time applications. This book proposes flexible and efficient architectures for DWT, matching arithmetic coder (MQ coder) and EBCOT units of the JPEG2000 system. The implemented parallel structure increases throughput off the Tier-1 (EBCOT and MQC) and DWT by factors of 301 and 164 cycles respectively. Execution results from software only and FPGA implemented JPEG2000 is compared and analyzed.

Seller Inventory # 9783838334769

Bibliographic Details

• Title: An Efficient Implementation of High-Speed JPEG2000 Encoder/Decoder : ALGORITHMS, SPECIFICATIONS, DESIGN SPACE EXPLORATION
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2010
• Language: English
• ISBN 10: 3838334760
• ISBN 13: 9783838334769
• Binding: Taschenbuch
• Condition: Neu

About this title

Synopsis

This book presents a complete and up-to-date description of an efficient FPGA implementation of high-speed JPEG2000 using formal design methodologies namely SpecC and A3, in a systematic and clear manner. JPEG2000 proposes a large set of advanced features for today's internet and multimedia applications. At the heart of JPEG2000 are two complex DSP algorithms: Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optmized Truncation (EBCOT). Both algorithms are complex, compute intensive and very difficult to optimize in software implementation for real-time imaging and multimedia applications. A hardware implementation brings a solution to this complexity for real-time applications. This book proposes flexible and efficient architectures for DWT, matching arithmetic coder (MQ coder) and EBCOT units of the JPEG2000 system. The implemented parallel structure increases throughput off the Tier-1 (EBCOT and MQC) and DWT by factors of 301 and 164 cycles respectively. Execution results from software only and FPGA implemented JPEG2000 is compared and analyzed.

About the Author

Michael Yaw Appiah have been researching into multimedia algorithm development and applications for more than 2 years. He is currently working as coordinator - RTX Telecom A/S with special interest on Video compression algorithms, radio network performance/optimisation for WCDMA/HSxPA. He received his M.Sc. from Aalborg University, Denmark in 2006.