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High Speed Dynamic Comparator for High Speed Adcs

Prasun Bhattacharyya

ISBN 10: 3659230723 / ISBN 13: 9783659230721
Published by LAP LAMBERT Academic Publishing
New Condition New Paperback
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Paperback. 76 pages. Dimensions: 8.7in. x 5.9in. x 0.2in.Comparators are most probably second most widely used electronic components after operational amplifiers in this world. Comparators are known as 1-bit analog-to-digital converter and for that reason they are mostly used in large abundance in AD converter. Dynamic comparators are being used in ADCs extensively nowadays because they are high speed, having zero static power consumption and provide full-swing digital level output voltage in lesser time duration. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources. Comparators are designed and simulated their DC response and Transient response in Cadence Virtuoso Analog Design Environment using GPDK 90 nm technology. Layouts of the proposed comparator have been done in Cadence Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated. This item ships from multiple locations. Your book may arrive from Roseburg,OR, La Vergne,TN. Bookseller Inventory # 9783659230721

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Synopsis:

Comparators are most probably second most widely used electronic components after operational amplifiers in this world. Comparators are known as 1-bit analog-to-digital converter and for that reason they are mostly used in large abundance in A/D converter. Dynamic comparators are being used in ADCs extensively nowadays because they are high speed, having zero static power consumption and provide full-swing digital level output voltage in lesser time duration. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources. Comparators are designed and simulated their DC response and Transient response in Cadence® Virtuoso Analog Design Environment using GPDK 90 nm technology. Layouts of the proposed comparator have been done in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated.

About the Author: I have completed my B.Tech in ECE from WBUT, KOLKATA in 2007. I have completed my M.Tech degree in VLSI Design and Embedded System from NIT Rourkela in 2011.

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Title: High Speed Dynamic Comparator for High Speed...

Publisher: LAP LAMBERT Academic Publishing

Binding: Paperback

Book Condition: New

Book Type: Paperback

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