Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures (Lecture Notes in Electrical Engineering, 184)

Ogras, Umit Y.; Marculescu, Radu

ISBN 10: 9400739575 / ISBN 13: 9789400739574

Published by Springer, 2013

About this Item

Seller Inventory # ABLIING23Apr0412070050589

Bibliographic Details

• Title: Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures (Lecture Notes in Electrical Engineering, 184)
• Publisher: Springer
• Publication Date: 2013
• Language: English
• ISBN 10: 9400739575
• ISBN 13: 9789400739574
• Binding: Hardcover
• Condition: New

About this title

Synopsis

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures.

In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

From the Back Cover

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures.

This book explores outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.