Robust Sram Designs and Analysis
Singh, Jawar; Mohanty, Saraju P.; Pradhan, Dhiraj
Sold by GreatBookPrices, Columbia, MD, U.S.A.
AbeBooks Seller since April 6, 2009
New - Soft cover
Condition: New
Quantity: Over 20 available
Add to basketSold by GreatBookPrices, Columbia, MD, U.S.A.
AbeBooks Seller since April 6, 2009
Condition: New
Quantity: Over 20 available
Add to basketThis book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.
This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.
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