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Routing Congestion in VLSI Circuits: Estimation and Optimization

Sachin Sapatnekar

1 ratings by GoodReads
ISBN 10: 1441940138 / ISBN 13: 9781441940131
Published by Springer
New Condition New Paperback
From BuySomeBooks (Las Vegas, NV, U.S.A.) Quantity Available: 20
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Paperback. 250 pages. Dimensions: 9.2in. x 6.1in. x 0.6in.This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-library-based VLSI circuits. This item ships from multiple locations. Your book may arrive from Roseburg,OR, La Vergne,TN. Bookseller Inventory # 9781441940131

About this title:

Synopsis:

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

From the Back Cover:

With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware.

Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design.

Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers.

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Bibliographic Details

Title: Routing Congestion in VLSI Circuits: ...

Publisher: Springer

Binding: Paperback

Book Condition: New

Book Type: Paperback

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