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A Sum-Of-Product Based Multiplication Approach For FIR Filters And DFT

Rajeev Kumar

ISBN 10: 3848486369 / ISBN 13: 9783848486366
Published by LAP LAMBERT Academic Publishing
New Condition New Paperback
From BuySomeBooks (Las Vegas, NV, U.S.A.) Quantity Available: 20
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Paperback. 64 pages. Dimensions: 8.7in. x 5.9in. x 0.1in.Discrete Fourier Transform (DFT) and Finite Impulse Response (FIR) filters are extensively used in Digital Signal Processing (DSP) and Image Processing. In this book, an arithmetic Sum-of-Product (SOP) based approach to implement area- and delay-efficient DFT and FIR filter circuits is presented. The proposed SOP based engine uses an improved column compression algorithm, and handles the sign of the input efficiently. The partial products of the computation are compressed down to two operands, which are then added using a single hybrid adder. The problem of synthesizing DFT and FIR filters circuits can also be cast as an instance of the Multiple Constant Multiplication (MCM) problem. RAG-n is one of the best known algorithms for realizing an MCM block with the minimum number of adders. For DFT coefficients, the proposed approach yields faster circuits (by about 12-13) with low area penalty (about 5), as compared to RAG-n. Significant speed-ups are also observed for a set of FIR filters with hard-to-implement coefficients. This item ships from multiple locations. Your book may arrive from Roseburg,OR, La Vergne,TN. Bookseller Inventory # 9783848486366

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Discrete Fourier Transform (DFT) and Finite Impulse Response (FIR) filters are extensively used in Digital Signal Processing (DSP) and Image Processing. In this book, an arithmetic Sum-of-Product (SOP) based approach to implement area- and delay-efficient DFT and FIR filter circuits is presented. The proposed SOP based engine uses an improved column compression algorithm, and handles the sign of the input efficiently. The partial products of the computation are compressed down to two operands, which are then added using a single hybrid adder. The problem of synthesizing DFT and FIR filters circuits can also be cast as an instance of the Multiple Constant Multiplication (MCM) problem. RAG-n is one of the best known algorithms for realizing an MCM block with the minimum number of adders. For DFT coefficients, the proposed approach yields faster circuits (by about 12-13%) with low area penalty (about 5%), as compared to RAG-n. Significant speed-ups are also observed for a set of FIR filters with hard-to-implement coefficients.

About the Author: Rajeev Kumar received his B. Tech. degree in Electronics and Communication Engg. from Indian Institute of Technology Guwahati, India in May 2007, and his Masters Degree in Computer Engg. from Texas A&M University in May 2013. From 2007 to 2010, he worked as Design Engineer at ARM, India. His research interests are in VLSI CAD and circuit design.

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Bibliographic Details

Title: A Sum-Of-Product Based Multiplication ...

Publisher: LAP LAMBERT Academic Publishing

Binding: Paperback

Book Condition: New

Book Type: Paperback

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