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IP-based design is inevitable, taking into account the complexities of today's electronic designs. One such IP core that plays an important role in IP-based designs is microprocessor core. Soft processor cores are delivered in RTL code and provide high flexibility for users. This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA, which runs at a very high clock frequency at around 350 MHz, whereas most processor cores released by FPGA vendors run at about 200 MHz. Improvement includes design and implementation of instruction and data caches. Mechanisms to allow non-cacheable memory access are also implemented. Interrupt support and exception handling is added as well, preparing the microprocessor core to host MMU-less operating systems such as uCLinux, and full Linux provided that MMU is also added to the processor core. Thorough verification of the added modules is heavily emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps.
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About the Author:
Mahdad Davari received his BSc in Computer Engineering from Azad University, Tehran, in 2005, and after spending some years in industry, he received his MSc in 2011 in Electrical Engineering with specialization in System-on-Chip design from Linköping University, Sweden. In this work, he addresses improvements to an FPGA processor (IP Core).
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- PublisherLAP LAMBERT Academic Publishing
- Publication date2012
- ISBN 10 3847341359
- ISBN 13 9783847341352
- BindingPaperback
- Number of pages136
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FPGA Optimized Processor: Cache and Exception Handling Implementation
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Book Description Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -IP-based design is inevitable, taking into account the complexities of today's electronic designs. One such IP core that plays an important role in IP-based designs is microprocessor core. Soft processor cores are delivered in RTL code and provide high flexibility for users. This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA, which runs at a very high clock frequency at around 350 MHz, whereas most processor cores released by FPGA vendors run at about 200 MHz. Improvement includes design and implementation of instruction and data caches. Mechanisms to allow non-cacheable memory access are also implemented. Interrupt support and exception handling is added as well, preparing the microprocessor core to host MMU-less operating systems such as uCLinux, and full Linux provided that MMU is also added to the processor core. Thorough verification of the added modules is heavily emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps. 136 pp. Englisch. Seller Inventory # 9783847341352
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FPGA Optimized Processor : Cache and Exception Handling Implementation
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Book Description Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - IP-based design is inevitable, taking into account the complexities of today's electronic designs. One such IP core that plays an important role in IP-based designs is microprocessor core. Soft processor cores are delivered in RTL code and provide high flexibility for users. This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA, which runs at a very high clock frequency at around 350 MHz, whereas most processor cores released by FPGA vendors run at about 200 MHz. Improvement includes design and implementation of instruction and data caches. Mechanisms to allow non-cacheable memory access are also implemented. Interrupt support and exception handling is added as well, preparing the microprocessor core to host MMU-less operating systems such as uCLinux, and full Linux provided that MMU is also added to the processor core. Thorough verification of the added modules is heavily emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps. Seller Inventory # 9783847341352
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FPGA Optimized Processor Cache and Exception Handling Implementation
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Book Description Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Davari MahdadMahdad Davari received his BSc in Computer Engineering from Azad University, Tehran, in 2005, and after spending some years in industry, he received his MSc in 2011 in Electrical Engineering with specialization in System. Seller Inventory # 5511264
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Book Description Condition: New. First Edition. First Edition thus. FPGA Optimized Processor by Mahdad Davari. ISBN:9783847341352. Collectible item in excellent condition. Seller Inventory # 3847341352
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