Surveys the latest research and field-proven techniques for every form of memory fault tolerance, including manufacturing, online, and field-related fault tolerance. Authors focus on practical circuit and design solutions.
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The state of the art in fault-tolerant RAM development and production.
Next-generation electronic devices require advanced new nanofabrication CMOS technologies—and, in these environments, today's processing techniques simply will not produce adequate yields. To improve RAM reliability without compromising performance, cost, or space requirements, engineers are turning to advanced fault-tolerant techniques. In this book, Kanad Chakraborty and Pinaki Mazumder survey the latest research and field-proven techniques for every form of memory fault tolerance, including manufacturing, online, and field-related fault tolerance. Coverage includes:
Chakraborty and Mazumder focus on practical circuit and design solutions, presenting extensive illustrations and explaining device physics and circuit design theory in a reader-friendly manner. They also provide a compendium of more than 500 research papers on memory fault tolerance and reliability. Whether you're a design engineer, test engineer, manufacturer, or researcher, this is a comprehensive resource for building next-generation RAM with next-generation reliability.
Modern Semiconductor Design SeriesAbout the Author:
KANAD CHAKRABORTY is currently Member of Technical Staff, Agere Systems Research (Communications Systems Technology Lab). He was formerly a software engineer and researcher with IBM's Electronic Design Automation Lab. His contributions include development of novel fault-tolerant memory architectures, algorithms for multiport memory testing, new design automation approaches, and neural network applications.
PINAKI MAZUMDER is Professor in the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor. His research interests include nanoelectronic and quantum electronic circuits and simulation, digital and analog testing, VLSI system design, and VLSI Layout Automation. He is a Fellow of IEEE. Mazumder and Chakraborty are co-authors of Testing and Testable Design of High-Density Random-Access Memories.
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Book Description Lebanon, Indiana, U.S.A.: Prentice Hall, 2002. Soft cover. Book Condition: New. No Jacket. This book is BRAND NEW Soft cover International edition with black and white printing. ISBN number & cover page may be different but contents identical to the US edition word by word. Book is in English language. Bookseller Inventory # ABE-9822118372
Book Description Prentice Hall PTR, 2002. Hardcover. Book Condition: New. Bookseller Inventory # DADAX0130084654