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Book Description Soft Cover. Condition: new. Seller Inventory # 9781461375616
Book Description Condition: New. Seller Inventory # 19494855-n
Book Description Condition: New. Seller Inventory # ABLIING23Mar2716030034014
Book Description Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest. Seller Inventory # 9781461375616
Book Description Condition: New. PRINT ON DEMAND Book; New; Fast Shipping from the UK. No. book. Seller Inventory # ria9781461375616_lsuk
Book Description Condition: New. Seller Inventory # 19494855-n
Book Description Paperback / softback. Condition: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days. Seller Inventory # C9781461375616
Book Description Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest. 208 pp. Englisch. Seller Inventory # 9781461375616
Book Description Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, o. Seller Inventory # 4195690
Book Description Condition: New. Series: Frontiers in Electronic Testing. Num Pages: 203 pages, biography. BIC Classification: THR; UGC; UYF. Category: (G) General (US: Trade). Dimension: 235 x 155 x 11. Weight in Grams: 326. . 2012. Softcover reprint of the original 1st ed. 1998. paperback. . . . . Seller Inventory # V9781461375616