Cmos/Bicmos Ulsi: Low-Voltage, Low Power (Prentice Hall Modern Semiconductor Design Series) - Hardcover

Yeo, Kiat Seng; Rofail, Samir S.; Goh, Wang-Ling

Hardcover

ISBN 10: 0130321621 ISBN 13: 9780130321626

Publisher: Prentice Hall, 2001

Synopsis

The advent of ultra-large-scale-integration (ULSI) technology, which has brought the possibility of tiny logic integrated circuits packed with millions of transistors, has highlighted the importance of complementary metal oxide semiconductor (CMOS) and bipolar complementary metal oxide semiconductor (BiCMOS) technologies. After looking at the history of semiconductors, Yeo (Nanyang Technological U., Singapore), Rofail (Tritech Consulting, Canada), and Goh (Nanyang Technological U., Singapore) move on to look at the different BiCMOS process technologies and discuss design considerations for achieving high performance devices. Further discussion includes considerations of future generations of circuits designed for ultra-low-voltage usage and explains how the uses of latches and flip-flops can be integrated into designs for further performance and efficiency. Annotation c. Book News, Inc., Portland, OR (booknews.com)

About this title

About the Author

KIAT-SENG YEO joined the School of Electrical and Electronic Engineering (EEE), Nanyang Technological University (NTU), Singapore in 1993. He is now the Sub-Dean of EEE, Principal Investigator of NTU's Integrated Circuit Technology Research Group, Program Manager of the System-on-Chip Flagship Project, Coordinator of the Integrated Circuit Design Research Group, Technical Chairman of the 8th and 9th International Symposium on Integrated Circuits, Devices and Systems, and a Technical Consultant. He holds six patents and published more than 100 articles in BiCMOS/CMOS integrated circuit design and technology.

SAMIR S. ROFAIL has been a teacher, researcher, and consultant in semiconductor and IC design for 20 years. From 1992 to 1999, he coordinated NTU's IC-Design group, leading intensive research on low-voltage, low-power BiCMOS/CMOS circuits. He is now a technical consultant in Waterloo, Canada.

WANG-LING GOH joined NTU in 1996. Her research interests are in the areas of silicon processing technologies, particularly the SOI structures, CMP and Copper. She holds one patent and has published over 30 articles in the above named areas.

From the Back Cover

CMOS/BICMOS ULSI presents state-of-the-art BiCMOS low-voltage, low-power design techniques for ULSI and giga-scale integration engineering, covering process integration, device modeling, and characterization. Discover the latest MOS and bipolar models; breakthroughs in copper metallization, isolation, and deep submicron processes; and new approaches to designing logic gates, latches, and flip-flops.

Excerpt. © Reprinted by permission. All rights reserved.

Preface

With advances in ultra-large-scale-integration (ULSI) technology, the industry is now on the brink of logic integrated circuits (ICs) packed with over 100 million transistors, whose device feature dimensions are far smaller than the wavelength of visible light. This trend, together with the never-ending demand for maximum speed and minimum power, has shaped a new arena in which the Complementary Metal Oxide Semiconductor (CMOS) and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technologies have found themselves gaining importance and attracting keen interest in digital, analog, and even radio-frequency IC design. This development has led many business leaders and market visionaries to predict that the best is yet to come, and the established trend will stay with us for a long time.

This book begins with an introductory chapter on the history of semiconductor devices and its evolution throughout the years. It also addresses the importance of low power design and how it affects the portability, reliability, cost, and even environment in very-large-scale-integration (VLSI) and giga-scale-integration (GSI) engineering. A thorough review of low-voltage, low-power design limitations in relation to the power supply voltage, threshold voltage, scaling, and interconnect wires is detailed. Chapter 1 concludes with the challenges facing future device and circuit designers, caused by the ongoing shrinking of device dimensions and the never-ending growing complexities of integrated circuits.

Upon introducing the basics of BiCMOS devices, chapter 2 moves on to describe the different key BiCMOS process technologies as well as discuss the design considerations for achieving high-performance BiCMOS devices. A review of various isolation technologies, new planarization methods for shallow trench isolation (STI) structures, and the latchup phenomenon are detailed in this chapter. A new characterization method for the 0.18-mm ultra-shallow STI CoSi2 CMOS test structures is also reported. Deep submicron processes such as that for the realization of polysilicon emitter BiCMOS structure, low-capacitance bipolar/BiCMOS devices, silicon-on-insulator (SOI) CMOS/BiCMOS VLSI, copper interconnects for deep submicron SOI CMOS/BiCMOS structures, and low-voltage, low-power CMOS/BiCMOS structures are also described in great depth. Finally, the chapter finishes with a discussion of the future trends and directions of the CMOS/BiCMOS processes.

In chapter 3, the fundamentals of both MOSFETs and bipolar junction transistors (BJTs) are provided before moving on to describing the main models of the MOS and BJT. The assumptions made while developing these models together with the models' performance in technologically scaled environment are highlighted and explained in detail. A separate section is devoted to the analytical and experimental characterization of the sub-half micron-MOS devices, the modeling of lateral pnp BJTs in the pMOSFET structures, and the trends and general features of the various device/process parameters of scaled pMOSFETs operating in a hybrid-mode environment. A methodology to construct a device model for a given wafer, using device characterization tools based on the successful retrieval of experimental data, is presented toward the last part of this chapter. The chapter ends with a summary of all models reviewed, which are the MOSFET SPICE models such as the LEVEL1, LEVEL2, and LEVEL3 models; BSIM1, BSIM2, and BSIM3 models; HSPICE Level 50 (Philip MOS9) model; EKV MOSFET model; bipolar SPICE models; Ebers-Moll model; Gummel-Poon model; modified Gummel-Poon model; MEXTRAM model; HICUM; and VBIC model.

Chapter 4 presents an in-depth analysis and the development of a new generation of CMOS/BiCMOS circuits for present and future VLSI and GSI requirements. Different circuit design concepts, ideas, and techniques are explained in detail to show how they are implemented to enhance the circuit performance (speed and/or power) or to balance these conflicting constraints to achieve a required specification. In ultra-low-voltage design, the output voltage swing of a logic gate cannot be compromised. Hence, in this chapter, much attention is devoted to full-swing CMOS/BiCMOS circuits and the inherent techniques such as bootstrapping and transient saturation. The merged BiCMOS, the multidrain/multicollector complementary BiCMOS, the quasi-complementary BiCMOS, the feedback BiCMOS, the Schottky BiCMOS/BiNMOS, the high-b BiCMOS, the transiently saturated BiCMOS, and the bootstrapping CMOS/BiCMOS circuits are also covered in depth. A comparative evaluation of the various CMOS/BiCMOS circuits and how they are being applied in a low-voltage, low-power environment is presented.

Even though chapter 4 covers a wide range of logic gates pertaining to low-voltage, low-power IC design, it is important to step up from the basic cell design to the circuit design. In that respect, latches and flop-flops, which are commonly found in synchronous and asynchronous systems, are described in chapter 5. This chapter starts with an introductory section to explain the need for low-power latches and flip-flops. It also profiles the basics of latches and flip-flops-their functionality, types, applications, design styles, and development through the years. Because latches and flip-flops are used to store logic values, the traditional measures of area, speed, and power dissipation are not exhaustive and are insufficient to access their quality. Hence, it becomes imperative to have a comprehensive set of quality measures to evaluate all aspects of a design decision. The quality measures described in this chapter are composed of four main measures-performance, power dissipation, area, and sensitivity to voltage/technology scaling. Finally, the chapter concludes with the various design styles such as dynamic, static, and semistatic used in single edge-triggered flip-flops, and double edge-triggered flip-flops.

In conclusion, this book provides an in-depth insight into the low-power design aspects of CMOS/BiCMOS technology, together with the most recent advances in the area. The information presented shall be extremely beneficial and valuable to students, instructors, circuit designers, engineers, scientists, and professors who are already working or about to embark in this very important field of portable integrated electronics.

Edition details

• Publisher: Prentice Hall
• Publication date: 2001
• Language: English
• ISBN 10: 0130321621
• ISBN 13: 9780130321626
• Binding: Hardcover
• Number of pages: 585