This first edtion book covers the key design problems of modeling, architectural tradeoffs, functional verification, timing analysis, test generation, fault simulation, design for testablility, logic synthesis, and post-synthesis verification. The author's focus is on developing, verifying, and synthesizing designs of digital circuits rather than on the Verilog language. Some of the topics covered in this book include Digital Design Methodology, Combinational Logic, Sequential Logic Design, Logic Design with Verilog,...
Behavioral modeling with a hardware description language (HDL) is the key to modern ASIC design. Readers preparing to contribute to a productive design team must know how to use a hardware description language at key stages of the design flow. This book is written for a course going beyond the basic principles and methods learned in a first course in digital design.
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