Timing Verification of Application-Specific Integrated Circuits - Hardcover

Nekoogar, Farzad

Hardcover

ISBN 10: 0137943482 ISBN 13: 9780137943487

Publisher: Prentice Hall, 1999

Synopsis

Reviewers tell us that Case/Fair is one of the all-time bestselling principles of economics texts because they trust it to be clear, thorough and complete.  This well-respected author team is joined for the 9^th edition by a new co-author, Sharon Oster.  Sharon’s research and teaching experience brings new coverage of modern topics and an applied approach to economic theory, as demonstrated in the new Economics in Practice feature.
Introduction to Economics; Concepts and Problems in Macroeconomics; The Core of Macroeconomic Theory; Further Macroeconomic Issues; The World Economy
For those looking for a trusted and authoritative principles of macroeconomics text that focuses on international econmies as well as the Keynesian Cross. Case/Fair/Oster believe strongly, that a text should use the Keynesian Cross carefully and systematically, to build up to the AD/AS model.  One of the great benefits of this approach, is that students of economics won’t mistakenly apply what they learned about simple demand and supply to aggregate demand & supply.  (A detailed summary of this approach can be found in the preface).

About this title

About the Author

FARZAD NEKOOGAR, formerly a Technical Manager at Intrinsix Corp., has extensive practical experience verifying timing of ASICs, FPGAs, and systems-on-a-chip. He is a lecturer at the University of California at Davis, and is the author ofDigital Control Using Digital Signal Processing, published by Prentice Hall PTR.

From the Back Cover

79434-7

It's About Time

In today's high-speed designs, timing analysis is critical to success. This is the first book to focus exclusively on these crucial timing issues, with special emphasis on timing verification of ASICs. Timing Verification of Application Specific Integrated Circuits (ASICs) highlights principles and techniques over specific tools. This method makes the materials applicable to a variety of logic design approaches, especially in the field of deep submicron digital design. Topics include:

• Clock definitions, multicycle paths, false paths, and phase-locked loops
• Behavioral and structural RTL coding for timing
• Timing analysis of FPGAs
• Pre and Post layout timing analysis
• Synthesis and Timing constraints
• EDA timing tools

Numerous design examples and Verilog codes offer practical illustrations of all the concepts. Timing Verification of Application Specific Integrated Circuits (ASICs) is a must for all logic designers concerned with the accuracy of timing and clock issues.

From the Inside Flap

Preface

This book describes the theory and applications of timing verification of application-specific integrated circuits (ASICs). Timing verification is a relatively new concept, which is why most books on digital systems do not cover the issue. This book lays out the fundamental principles of effective timing verification, and it makes good use of the examples that reflect the current issues facing logic designers.

The following items characterize this book:

Timing verification as opposed to functional verification is the primary focus. (Functional simulation has been adequately covered in other books.)Principles and techniques as opposed to specific tools are emphasized. Once designers understand the underlying principles of timing analysis, they can apply them with various timing tools.Design flow for deep-submicron ASICs and FPGA designs are fully covered.Numerous design examples and HDL codes to illustrate the concepts discussed in the book are provided.

This book is to be used for self-study by practicing engineers. Design and verification engineers who are working with ASICs and FPGAs will find the book very useful. Upper-level undergraduate and graduate students in electrical engineering can use it as a reference book in design courses in timing analysis and related topics.

The material covered in this book requires some understanding of the Electronic Design Automation (EDA) tools and an initial course in logic design.

The book is organized into two parts:

Part I (chapters 1 and 2) introduces the fundamental concepts involved in timing verification. Including clock definitions, multicycle paths, false paths, and phase-locked loops.

Part II (chapters 3 and 4) covers specific timing issues related to ASICs and FPGAs, respectively.

Chapter 1 gives an overview of timing verification and static timing analysis. It contrasts timing verification with functional verification. Typical goals of timing verification in digital systems are presented. This chapter ends with an example of interface timing analysis.

Chapter 2 introduces the concepts of timing analysis with design examples. It specifically discusses such clocking methods as gated clocks, multifrequency clocks, and multiphase clocks. It introduces the concepts of multicycle paths, false paths, and timing constraints (such as setup, hold, recovery, and pulse width).

Chapter 3 discusses the deep submicron ASIC design flow and application of timing analysis in the design process. It includes discussion of prelayout and postlayout timing verification. The chapter also discusses behavioral and structural RTL coding for timing, synthesis and timing constraint, and the ASIC sign-off checklist. We make the concepts concrete with numerous examples.

Chapter 4 discusses timing concepts in programmable logic-based designs. It covers design flow, timing parameters, timing analysis, and HDL synthesis and software development systems. We present the most commonly used programmable logic devices (Actel, Altera, and Xilinx) and associated timing issues.

Appendices A, B, and C discuss the EDA timing tools of PrimeTime, Pearl, and TimingDesigner respectively.

Appendix D covers some concepts of transistor-level timing verification.— Farzad Nekoogar

Edition details

• Publisher: Prentice Hall
• Publication date: 1999
• Language: English
• ISBN 10: 0137943482
• ISBN 13: 9780137943487
• Binding: Hardcover
• Edition number: 1
• Number of pages: 179