Verilog Styles for Synthesis of Digital Systems

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9780201618600: Verilog Styles for Synthesis of Digital Systems

This book is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to those just entering the field. The text uses a simpler language (Verilog) and standardizes the methodology to the point where even novices can get medium complex designs through to gate-level simulation in a short period of time. Requires a working knowledge of computer organization, Unix, and X windows. Some knowledge of a programming language such as C or Java is desirable, but not necessary. Features a large number of worked examples and problems--from 100 to 100k gate equivalents--all synthesized and successfully verified by simulation at gate level using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx. Basic Language Constructs. Structural and Behavioral Specification. Simulation. Procedural Specification. Design Approaches for Single Modules. Validation of Single Modules. Finite State Machine Styles. Control-Point Writing Style. Managing Complexity--Large Designs. Improving Timing, Area, and Power. Design Compiler. Synthesis to Standard Cells. Synthesis to FPGA. Gate Level Simulation and Testing. Alternative Writing Styles. Mixed Technology Design. For anyone wanting an accessible, accelerated introduction to the cutting-edge tools for Digital Hardware Design.

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From the Inside Flap:

Preface

In the last few years, the way that digital hardware is designed has undergone a reinvention. On one hand, manual design with schematic entry tools has been replaced by synthesis from high level specifications. On the other hand, custom integrated circuits are being supplanted by field programmable gate arrays (FPGA) for many applications. This text seeks to help students take their place in this new environment by making it more accessible.

Currently hardware synthesis is complex and not at all like the software compilation to which it is superficially analogous. It might take a competent hardware designer a year or more to become fluent in this technology. The subsets of the two broad-based hardware description languages in current use, Verilog and VHDL, permit myriad different specifications of even the simplest module, with structural and behavioral constructs intermixed at will. Each different description may give a different result and presents different synthesis problems. What is needed is another standardization and simplification like that of Mead and Conway, which availed an earlier VLSI technology to a wider group of users. This book tries to do this by selecting the simpler language, Verilog, and standardizing the methodology to the point where seniors and first-year graduates can see medium to complex designs through to gate-level simulation in a single semester. The text is neither a complete description of the Verilog language, nor simulation, nor synthesizers, nor FPGA chip fitting tools. For these, the reader should consult the large numbers of corresponding manuals. However, using this text, together with the example tools, students can and do get interesting projects working in a single semester course. This could be a semester well spent since the demand from industry for people with this knowledge seems to exceed even that for systems software expertise. After this, with the confidence of having navigated a complete pass through the process, readers can graduate to more esoteric designs and consult the many available manuals at their leisure.

There are several other good books in this general area. Of recent ones, we mention a few:

First Smith97 (no relation) is an outstanding encyclopedic reference on all matters to do with ASICS. Here the emphasis is on schematic design, layout, and device physics supplemented by specifications in VHDL or Verilog. Then there are books such as Palnitkar96, Arnold99, and Ciletti99 concentrating specifically on the Verilog language itself. In all of the above, the pedagogical approach has really been to go first through all the language constructs in Verilog available to simulation, and then present the limitations of synthesis afterwards. This is to be contrasted with our treatment in which synthesis issues are introduced from the outset, incorporated into the material throughout, and designed to get students working with synthesis early.

Next there are some works aimed at an audience already familiar with high-level design methodology and more oriented to specialized reference. Karup97 is really a compendium of tips and case studies in VHDL/Verilog and Synopsys with the corresponding solutions; Keating98 contains tool usage and style recommendations, specifically for modules intended for reuse in the intellectual property market, but without working examples. So these are more suitable as supplements to some other basic text.

We should also mention the series of books on synthesis by Gajski and Micheli. These are a different kind of book, more oriented to research in the area, and to the few who will design the synthesizers, rather than to the many who will use them to create practical designs and get a job.

Yet there is still no book that covers style recommendations specifically oriented to synthesis, that is illustrated with practical working examples, and that is accessible to the reader who wants to get a start in this field. This is a void that needs to be filled and we are hopeful that this book may do so. All the worked examples and the problems at the end of each chapter have been synthesized and successfully verified by simulation at gate level. The material has been tested in classes over three years aimed at seniors and first-year graduate students having a prerequisite of an introductory course in computer organization and a working knowledge of Unix and X windows. At the moment most industrial designers still prefer this environment, although the tools are now becoming available in the NT and Linux environments.

Synthesis and fitting tools are usually available to universities at nominal maintenance fees under vendors' "university programs." Sometimes a simulator is packaged with a tool suite, sometimes not. In what follows, the exercises have been worked out using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx. Of course this is somewhat specific and the reader's location may be committed to alternative tools. We would have really liked to have compared synthesizers available from other vendors. There is really no good solution to this, since even at university pricing, any one site (including ours) cannot afford all the alternatives, nor commit the time and resources involved. All we can do is try to choose some of the best tools currently available and trust that many of the issues faced by users in other environments will be similar. For example even though Verilog and VHDL are rather different, the subsets used for synthesis by the major vendors are quite similar at the moment, which is why automatic translators are available. A complete list of vendors offering tools in the separate areas relevant to this book, such as simulation, synthesis, and FPGA, are listed at regular intervals in trade magazines including Integrated System Design (isdmag). Here the interested reader can gain ready access to the vendor representatives or Web pages to discover the relative advantages of the tools and what is available in the various university programs.

The material of this book is suitable for seniors or first-year graduate students who have had an introduction to Boolean algebra and computer organization. A working knowledge of Unix and X-windows is necessary for the exercises. Some knowledge of a programming language such as 'C' or Java is desirable but not necessary. We usually find that students from a computer science background come to the course with more intuition of the software while students from an electrical engineering background bring more of a intuition on gate networks. So the two arrive at the course with about the same potential to start in on this material.

We should give some explanation of the ordering of the chapters, which might seem a little peculiar at first. This is one of those subjects in which students learn by doing. Accordingly, our approach has been to introduce the use of the simulator and then the synthesizers at the earliest practical point. In this way the students should be able to ramp up on the tool learning curve and follow a trial run of a small design all the way through high-level simulation, the design compiler, FPGA, fitting, and gate-level simulation by about the middle of the semester. With this under their belts, they will be better psychologically prepared to move onto a larger independent project, the behavioral compiler, or download to and test real hardware in the time remaining to them. Thus the ordering we have chosen may be at the cost of breaking the continuity of the treatment of the design language and the examples of specification. If the user of this book disagrees with this philosophy, there is al4ays the option of reordering the chapters accordingly, say by delaying the introduction of simulation of Chapter 4 until the Chapter 7 on validation, or bringing the chapters on specification (3, 5 through 9) together, or by bringing together the sections on testing and debugging from Chapters 4, 7, and 15), or by bringing the materials on the design compiler and the behavioral compiler (Chapters 12, 13, and 16) together before proceeding to the FPGA targeting.

For readers who want to try the examples, refer to the home page prepared for the Prentice Hall site at the url prenhall/smith/franzon.

From the Back Cover:

The material available within this book is suitable for professionals who have had an introduction to Boolean algebra and computer organization. A working knowledge of Unix and X-windows is necessary, along with some experience with programming languages such as 'C' or Java. The book uses Verilog and standardizing methodology to such a degree that seniors and first year graduate students can see medium complex designs through the gate level simulation in a single semester.

Features:

  • The piece covers style recommendations specifically oriented to synthesis, illustrated with practical working examples, and easily accessible to the reader.
  • It introduces the use of the simulator and then the synthesizers at the earliest practical point; therefore giving the reader the perspective of working with a small design all the way through high level simulation.
  • Large number of examples; from 100-100k gate equivalents.
  • Topics covered include; Synopsys, Altera, Xilinx, and the standard cell.

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