Firewire System Architecture: IEEE 1394 (PC System Architecture Series) - Softcover

Don-anderson-inc-mindshare

Softcover

ISBN 10: 0201694700 ISBN 13: 9780201694703

Publisher: Addison-Wesley Professional, 1998

Synopsis

FireWire (IEEE 1394) is an emerging technology that provides high-speed serial bus communications. This book offers an in-depth overview of the IEEE 1394 cable environment based on the 1394-1995 release of the standard and includes changes introduced by the 1394a supplement. IEEE 1394 defines a layered software and hardware approach for serial bus communications. This book details the various layers and provides transaction examples to explain and illustrate the relationships between each layer. It explores important features of 1394 including:

* Node architecture * Address space * Arbitration * Transaction types: isochronous, asynchronous, lock * Broadcast transactions * Control and status registers (CSRs) * Automatic configuration * Configuration ROM * Bus management * Physical layer * Transaction layer * Link layer * Cable and electrical interface Comprehensive, concise, and well-organized, this book is an essential resource and reference for anyone who designs or tests hardware or software involving FireWire( (IEEE 1394) technology.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware, and thoroughly explains the architecture, features, and operation of systems built using one particular type of chip or hardware specification.

About this title

From the Inside Flap

About This Book The MindShare Architecture Series

The MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, Pentium Pro and Pentium II System Architecture, USB System Architecture, FireWire System Architecture and AGP System Architecture. The book series is published by Addison-Wesley. Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which the others build. Cautionary Note

The reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. With IEEE 1394, this is particularly true. This book is based in part on several incomplete specifications. This being the case, it should be recognized that the book is a "snapshot" of the state of 1394 technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the specification to be "frozen," the time necessary to make the changes, and the time to produce the books and get them out through the distribution channels), there will always be a delay.

Please check our web site for additions and errata on this and other MindShare books. As specifications and technologies change MindShare maintains errata, clarifications, and additions to the books to ensure that the reader has a way of keeping updated on recent developments (mindshare). Organization of This Book

The book is divided into six parts and an appendix. Each part contains the chapters listed below and a brief description of the contents of each chapter. Part One: Introduction to FireWire (IEEE 1394) Chapter 1: Why FireWire?

This chapter describes background information regarding the development of the FireWire specification (1394-1995 and the 1394a Supplement) and discusses FireWire applications. Chapter 2: Overview of the FireWire Architecture

This chapter describes the primary features of the FireWire serial bus implementation. The chapter also reviews the IEEE 1394 standards (IEEE 1394-1995 & IEEE 1394a) and IEEE ISO/IEC 13213 (ANSI/IEEE 1212) standard that the FireWire serial bus is based upon. Part Two: Serial Bus Communications Chapter 3: Communication Model

This chapter provides an overview of the serial bus communications model. It defines the basic transfer types and introduces the communication layers defined by the specification. Chapter 4: Communications Services

This chapter describes the services defined by the specification that are used to pass parameters between layers during the execution of each transaction. The protocol layers and services for asynchronous and isochronous transactions are discussed. Asynchronous transactions exist in three forms: reads, writes, and locks, while isochronous transactions are performed only as writes. Chapter 5: Cables & Connectors

This chapter discusses the cable characteristics and connectors used by the IEEE 1394 cable environment. It also mentions the Device Bay implementation being specified in PC environments. Chapter 6: The Electrical Interface

This chapter details the serial bus signaling environment. This includes recognition of device attachment and removal, arbitration signaling, speed signaling, and data/strobe signaling. Chapter 7: Arbitration

This chapter details the arbitration process. It defines the various types of arbitration including isochronous and asynchronous arbitration, as well as the newer arbitration types defined by the 1394a supplement. Chapter 8: Asynchronous Packets

Asynchronous transactions exist in three basic forms: reads, writes, and locks. This chapter details the packets that are transmitted over the bus. Chapter 9: Isochronous Packets

Isochronous transactions are scheduled so that they occur at 125us intervals. This chapter discusses the format of the packet used during isochronous transactions. Chapter 10: PHY Packet Format

This chapter discusses the various types of PHY packet. The role of each PHY packet is discussed, packet format is specified, and the fields within each packet are detailed. Chapter 11: Link to PHY Interface

This chapter details the signaling interface between the link and PHY layer controller chips. The 1394a supplement makes this interface mandatory for implementations of separate PHY and link layer chips. Chapter 12: Transaction Retry

This chapter discusses transaction retries that occur when the recipient of a packet is busy (e.g. has a buffer full condition). Two retry mechanisms are defined by the 1394 specification: single and dual phase. Each type of mechanism is discussed. Software may also initiate retries for transactions that fail. Part Three: Serial Bus Configuration Chapter 13: Configuration Process

This chapter overviews the configuration process comprising the initialization, tree ID, and self-ID phases. Once self-ID completes, additional configuration may optionally take place in the form of bus management activities that are also reviewed in this chapter. Chapter 14: Bus Reset (Initialization)

This chapter details the bus reset phase of the cable configuration process. Initialization begins with the assertion of a bus reset by a given node on the bus. This chapter discusses the reset enhancements introduced by the 1394a supplement; debouncing the bias change detection, arbitration (short) bus reset, and new timing parameters. Chapter 15: Tree Identification

Following bus initialization, the tree ID process begins to determine which node will become the root. This chapter details the protocol used in determining the topology of the serial bus. Chapter 16: Self Identification

This chapter focuses on the self-ID process. During self-ID all nodes are assigned addresses and specify their capabilities by broadcasting self-ID packets. Part Four: Serial Bus Management Chapter 17: Cycle Master

This chapter describes the role of the cycle master node, and defines how the cycle master is identified and enabled. Chapter 18: Isochronous Resource Manager

This chapter describes the role of the isochronous resource manager: how it is identified and enabled, and how other nodes interact with it. Chapter 19: Bus Manager

In this chapter, the bus manager function is described including topology map and speed map generation and access, as well as power management. Chapter 20: Bus Management Services

This chapter discusses the bus management services used by the bus manager and isochronous resource manager to perform their bus management roles. Part Five: Registers and Configuration ROM Chapter 21: CSR Architecture

This chapter discusses the CSR registers defined by the ISO 13213 specification with particular focus on the registers that are required by the 1394 specification. Chapter 22: PHY Registers

This chapter introduces the PHY register map and port registers. Both the 1394-1995 and the 1394a PHY registers are detailed. Chapter 23: Configuration ROM

This chapter details the contents of configuration ROM required by the ISO/IEC 13213 specification. The serial bus also defines ROM entries that are required by some nodes, depending on the capabilities. Part Six: Power Management Chapter 24: Introduction to Power Management

This chapter provides a brief introduction to the power management environment introduced by the 1394a specification. The chapter introduces the three documents that further define the power management specification: Cable Power Distribution, Suspend/Resume Mechanisms, and Power State Management. Chapter 25: Cable Power Distribution

This chapter discusses power distribution in the cable environment. It discusses the four power types designations for nodes: power providers, alternate power providers, power consumers, and self-powered devices. Details regarding the power implementation of nodes in also included. Chapter 26: Suspend & Resume

This chapter introduces the suspend and resume mechanisms. This capability allows the PHY layer within a node to enter a low power state under software control (either local node software or from another node). The mechanisms implemented for suspend and resume are detailed including: command and confirmation packets, suspend initiator actions, suspend target actions, and related suspend and resume signaling. The impact on PHY and port register definition is also discussed. Chapter 27: Power State Management

This chapter describes the CSR registers and ROM entries that define power management capabilities and provide the mechanisms for controlling the power states of a node and of local units within a node. Appendix Example 1394 Chip Solutions

This chapter is provided by Texas Instruments and discusses a variety of 1394 component implementations. Target Audience

This book is intended for use by hardware and software design and support personnel. Due to the clear, concise explanatory methods used to describe each subject, personnel outside of the design field may also find the text useful. This book is perhaps best used prior to reading the IEEE 1394-1995 specification and 1394a Supplement. It provides the important context, concepts, and relationships that are essential for understanding the specifications. Prerequisite Knowledge

The reader should be familiar with computer architectures. Documentation Conventions

This document contains conventions that are used in other MindShare books and in the IEEE 1394 documentation. Since this book is a companion to the specification, many of the standard documentation conventions are used here to ease the transition between the two documents. Labels for Multi-byte Blocks

The CSR Architecture and the IEEE 1394 standards attempt to eliminate confusion of terminology relating to the terms: word as it applies to the size of an aligned block of bytes in address space. Depending on the manufacturer, a "word" may refer to 2 bytes or to 4 bytes. The IEEE standards chooses to define multibytes as follows:
nibble (4-bits)
byte (8-bits)
doublet (two bytes)
quadlet (four bytes)
octlet (eight bytes)
Hexadecimal Notation

This section defines the typographical convention used throughout this book. Hex Notation All hex numbers are followed by an "h." Examples:
9A4Eh
0100h
Binary Notation

All binary numbers are followed by a "b." Examples:
0001 0101b
01b
Decimal Notation

Numbers without any suffix are decimal. When required for clarity, decimal numbers are followed by a "d." The following examples each represent a decimal number:
16
255
256d
128d
Bits versus Byte Notation

This book employs the standard notation for differentiating bits versus bytes. All abbreviations for "bits" use lower case. For example:
1.5Mb/s
2Mb

All references to "bytes" are specified in upper case. For example:
10MB/s
1KB
Identification of Bit Fields (logical groups of bits or signals)

All bit fields are designated in little-endian bit ordering:
X::Y,
where "X" is the most-significant bit and "Y" is the least-significant bit of the field. Visit Our Web Site

Our web site contains a listing of all of our courses and books. In addition, it contains errata for a number of the books, a hot link to our publisher's web site, and course outlines: mindshare. We Want Your Feedback

MindShare values your comments and suggestions. You can contact us via mail, phone, fax, or internet e-mail.
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From the Back Cover

Praise for the first edition:

"Finally, a book on IEEE 1394 that's easy to understand!!! MindShare's FireWire System Architecture: IEEE 1394 provides a consolidated learning tool for 1394 hardware and software, and confirms the statement, '1394's for the fun stuff....'"
-Phil Roden, 1394 Digital Design Manager, Texas Instruments

The FireWire (IEEE 1394a) standard for high-speed serial bus communications has come to the fore as an important technology supporting today's emerging data-intensive applications.

FireWire System Architecture provides an in-depth description of the IEEE 1394a cable environment, based on the 2.0 version of the 1394a standard. Comprehensive, concise, and well-organized, this book details the specification itself and presents the architecture, features, and operations of systems developed with the FireWire bus. Completely up-to-date, this new edition covers all of the changes incorporated into the 2.0 standard, such as arbitration enhancements, improvements in bus reset timing, new PHY register definition, and port interface enhancements to support suspend/resume and port disable. In addition, it provides in-depth information on suspend/resume operation, power distribution, and power management.

FireWire System Architecture describes the various hardware and software layers that make up the FireWire serial bus and provides transaction examples to explain and illustrate the relationship between each layer.

It explores such essential topics as:

• The communications model
• Asynchronous and isochronous transactions
• Cables and connectors
• The electrical interface
• Asynchronous and isochronous arbitration, including such enhancements as fly-by arbitration, acceleration control, and priority arbitration service
• Packets, including the PHY packet format
• Serial bus configuration and management
• Control and status registers (CSRs)
• Configuration ROM
• Power management

Numerous sample implementations throughout the book demonstrates how theory is put to use in real-world applications. This combination of comprehensive reference, readable explanation, and examples make this guide indispensable for anyone who works with the IEEE 1394a technology.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware, and thoroughly explains the architecture, features, and operation of systems built using one particular type of chip or hardware specification.

Edition details

• Publisher: Addison-Wesley Professional
• Publication date: 1998
• ISBN 10: 0201694700
• ISBN 13: 9780201694703
• Binding: Paperback
• Language: English
• Number of pages: 416