Items related to Testing Semiconductor Memories: Theory and Practice
Comprehensive coverage of memory test problems at chip, array and board level is provided in this book. For each of these test levels a class of fault models is introduced along with tests for these models. The author also presents algorithms of relevant fault models, together with proofs of their correctness. Special attention is given to why a fault model belongs to a particular class and why it is of interest. A software package, suitable for use on IBM PCs and compatibles,is also available which consists of a set of memory test programs and a simulation package demonstrating how the algorithms are executed and the relationship of the algorithm with the memory.
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From the Publisher:
As the size and density of semiconductor memories are increasing rapidly, testing them is becoming a major concern. This book tries to bring order to the vast amount of material published in the field by introducing a framework for ordering fault models and covering those test algorithms which are considered most efficient for finding the faults of each fault model. It presents memory test problems on the chip, array and board level, introducing fault models and tests for them at each of those levels.
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- PublisherJohn Wiley & Sons
- Publication date1991
- ISBN 10 047192587X
- ISBN 13 9780471925873
- BindingPaperback
- Number of pages512
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