Synopsis
This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as – the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers – optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations – design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors – state-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.
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About the Author
Jean-Loup Baer is Professor Emeritus of Computer Science and Engineering at the University of Washington, where he has been since 1969. Professor Baer is the author of Computer Systems Architecture and more than 100 refereed papers. He is a Guggenheim Fellow, an ACM Fellow, and an IEEE Fellow. Baer has held several editorial positions, including editor-in-chief of the Journal of VLSI and Computer Systems and editor of the IEEE Transactions on Computers, the IEEE Transactions on Parallel and Distributed Systems, and the Journal of Parallel and Distributed Computing. He has served as General Chair and Program Chair of several conferences, including ISCA and HPCA.
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