Items related to Introduction to Verilog
Synopsis
Hardware Description Languages (HDLs) use statements, like programming language statements, in order to define, simulate, synthesize, and layout hardware. One of the main HDLs is Verilog, a widely used and standardized language. Verilog can be used to design anything from the most complex ASIC to the least complex PAL. As ASICs and FPGAs become more complex, HDLs become a necessity for their design. This course teaches how to use Verilog to design and simulate hardware. It begins by explaining the benefits of HDLs over other design entry methods, including its ability to model different levels of abstraction, its reusability, and documentability. Next, the syntax of the Verilog language is explained in detail. By the end of the course, you will be able to design and simulate real hardware using Verilog. The course includes the study guide, final exam, the textbook Verilog Designer s Library (Prentice Hall, 1998) and one CD-ROM containing simulation software from Simucad, synthesis software from Synopsys and all of the code examples from the book. Upon successful completion the student receives 8 CEUs and a Certificate of Educational Achievement from the Institute of Electrical and Electronics Engineers.
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About the Author
Bob has nearly two decades of experience designing integrated circuits and circuit boards for many different types of systems. His clients have included Apple Computer, Cisco Systems, Ikos Systems, and Texas Instruments. He has written numerous technical papers on hardware and software design methods, authored a textbook entitled Verilog Designer's Library published by Prentice-Hall, and has instructed courses at engineering conferences throughout the world. He earned a master's degree in electrical engineering from Stanford University and two bachelor's degrees, in physics and electrical engineering, from Cornell University.
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This self-study guide came about as the result of the popularity of my textbook, Verilog Designer s Guide. That book is an intermediate to advanced level reference book about the Verilog Hardware Description Language. The book has a lot of good advice and a large number of well-documented Verilog routines that can be used to create real-world hardware. Shortly after its publication, the Institute of Electrical and Electronics Engineers (IEEE) approached me to create a study guide based on the book. I realized that for those who already knew Verilog, the book was fairly self-explanatory. However, it could be difficult to navigate for those who are just learning. Yet the functions in the book make ideal examples and problems for learning the language. With that in mind I decided to create this introductory study guide using my textbook for illustration and problem assignments. This study guide is based on the Verilog seminar that I give around the world. Over the years ! I ve used the feedback from students to try to make this the best introductory Verilog course available. I hope I ve succeeded. If you want to comment, either to congratulate me on the excellent job I ve done, to ask a question, to point out a mistake or misconception, or to suggest improvements for the future, or simply to complain, please do so. I welcome all feedback.
Course Objectives
Hardware Description Languages (HDLs) use statements, like programming language statements, in order to define, simulate, synthesize, and layout hardware. One of the main HDLs is Verilog, a widely used and standardized language. Verilog can be used to design anything from the most complex ASIC to the least complex PAL. As ASICs and FPGAs become more complex, HDLs become a necessity for their design.
This course teaches how to use Verilog to design and simulate hardware. It begins by explaining the benefits of HDLs over other design entry methods, including its ability to model different levels of abstraction, its reusability, and documentability. Next, the syntax of the Verilog language is explained in detail. By the end of the course, the student should be able to design and simulate real hardware using Verilog.
Intended Audience
The book is aimed at electrical engineering students and practicing electrical engineers who are not yet familiar with Verilog. It is intended for engineers who wish to cover a lot of ground toward understanding and using Verilog to create real designs. The prerequisite is a good knowledge of digital logic design. Knowledge of programming languages, such as C or C++, and knowledge of other Hardware Description Languages (HDLs) such as VHDL, is beneficial but not mandatory.
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