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Synopsis
Learn all the intricacies of the design of a 32-bit RISC microprocessor developed through the first DARPA effort to create a 200 MHz processor on a VLSI chip. This book takes you through all phases of this project and covers all the theoretical and technical details necessary for the creation of the final architecture and design. It places special emphasis on the research and development methodology utilized in the project.
The methodology described in this book includes the following elements: creation of a candidate architecture, comparative testing on the functional level, selection and final refinement of the best architecture, transformation from the architecture level to the design level, logical and timing testing of the design, and presentation for fabrication. The text details how software tools are used in this project and how RISC architecture serves as the baseline for the project. It covers specific design techniques, languages, testing phases, architectural issues, implementation technology, and applications. The book, tested in a number of university courses and commercial tutorials, is ideal for various undergraduate courses devoted to microprocessor design for VLSI.
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Surviving the Design of a 200 RISC Microprocessor : Lessons Learned
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Surviving the Design of a 200 Mhz Risc Microprocessor: Lessons Learned
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Surviving the Design of a 200 Mhz Risc Microprocessor: Lessons Learned
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Surviving the Design of a 200 Mhz Risc Microprocessor: Lessons Learned
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Institute of Electrical & Electronics Enginee, 1998
ISBN 10: 0818673435
ISBN 13: 9780818673436
Used
Paperback
Seller: Sunny Day Books, Mayer, AZ, U.S.A.
Seller rating 5 out of 5 stars
Paperback. Condition: As New. A very nice copy. Text in mint/unmarked condition. Cover has minor shelf rubbings. Binding is tight. Seller Inventory # E6C0020144