Synopsis
Reports research promoting a better design approach to testing integrated circuits based on high-level test synthesis, which is able to explore the synthesis freedom provided at a high level to derive an inherently testable architecture at low or even no overhead. Presents several effective schemes for highly testable digital circuits, assuming a non-scan or partial-scan test strategy. These schemes are implemented in the Princeton HI- level Test Synthesis system, which is also presented. Based on a Ph. D. dissertation for Princeton. Double spaced. Annotation c. by Book News, Inc., Portland, Or.
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About the Author
Mike Tien-Chien Lee earned his Ph.D. in electrical engineering from Princeton University and is currently a member of the research staff at Fujitsu Laboratories of America, Inc., Santa Clara, California.
"About this title" may belong to another edition of this title.
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High-Level Test Synthesis of Digital VLSI Circuits (Artech House Solid-State Technology Library)
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High-Level Test Synthesis of Digital VLSI Circuits
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