Synopsis
Explaining how HTS is able to explore the synthesis freedom provided at high-level to derive an inherently testable architecture at low or even no overhead, this text provides an introduction to HTS and helps develop an understanding of this emerging technology by presenting a background of HTS terms, operation scheduling and resource allocation algorithms. The book also covers various HTS techniques for scan and built-in self-test methodologies, register-transfer level test synthesis, examples of several effective HTS schemes for highly testable digital circuits, and more.
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About the Author
Mike Tien-Chien Lee earned his Ph.D. in electrical engineering from Princeton University and is currently a member of the research staff at Fujitsu Laboratories of America, Inc., Santa Clara, California.
"About this title" may belong to another edition of this title.
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High-level test synthesis of digital VLSI circuits. The Artech House solid-state technology library.
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High-Level Test Synthesis of Digital VLSI Circuits (Artech House Solid-State Technology Library)
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High-Level Test Synthesis of Digital VLSI Circuits
Published by
Artech House Publishers, 1997
ISBN 10: 0890069077
ISBN 13: 9780890069073
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