Items related to A Verilog Hdl Primer
Synopsis
- Written for new users. - Explains the language through simple examples. - Explains the syntax of language using commonly-used design terminology. - Explains the behavioral style, the dataflow style, and structural style in detail. - Concepts of delay and timing are clearly explained. - Testbench writing is made easier by providing a number of examples. - Many hardware modeling examples have also been provided to make this an excellent reference.
Also includes exercises for every chapter and expanded coverage of more language features including test bench writing strategies.
Third edition is based on IEEE Verilog 2001 Standard. It includes explanations of all the new features introduced in this version of the language, with examples.
"synopsis" may belong to another edition of this title.
From the Back Cover
With this book, you can:
- Learn Verilog HDL the fast and easy way. - Obtain a thorough understanding of the basic building blocks of Verilog HDL. - Find out how to model hardware. - Find out how to test the hardware model using a test bench.
"This text is a definitive learning resource for the student of Verilog as well as an excellent reference for the experienced designer. The features of Verilog are clearly covered with both explanations and examples. Especially beneficial is Appendix A which contains a syntax reference in alphabetical order" - Vincent Zeyak Jr., Agere Systems
"I have found the book easy to read, to the point, and an excellent reference" - Sharad Seth, University of Nebraska at Lincoln
About the Author
Bhasker is an Architect at eSilicon Corporation. He was a Distinguished Member of Technical Staff at Bell Laboratories, Lucent Technologies. He has taught VHDL and Verilog HDL courses at Lucent Technologies for more than four years. He has also authored four other books in hardware description languages and synthesis including the best-selling books "A VHDL Primer" and "A VHDL Synthesis Primer". Bhasker has a PhD in Computer Science from the University of Minnesota, M.Tech. in Computer Technology and a B.Tech. in Electrical Enginering from the Indian Institute of Technology, New Delhi. TABLE OF CONTENTS: Preface xv Chapter 1 Introduction
1.1. What is Verilog HDL?,
1.2. History,
1.3. Major Capabilities,
1.4. Exercises, Chapter 2 A Tutorial
2.1. A Module,
2.2. Delays,
2.3. Describing in Dataflow Style,
2.4. Describing in Behavioral Style,
2.5. Describing in Structural Style,
2.6. Describing in Mixed-design Style,
2.7. Simulating a Design,
2.8. Exercises, Chapter 3 Language Elements
3.1. Identifiers,
3.2. Comments,
3.3. Format,
3.4. System Tasks and Functions,
3.5. Compiler Directives,
3.5.1. `define and `undef,
3.5.2. `ifdef, `ifndef, `else, `elsif and `endif,
3.5.3. `default_nettype,
3.5.4. `include,
3.5.5. `resetall,
3.5.6. `timescale,
3.5.7. `unconnected_drive and `nounconnected_drive,
3.5.8. `celldefine and `endcelldefine,
3.5.9. `line,
3.6. Value Set,
3.6.1. Integers,
Simple Decimal Form,
Base Format Notation,
3.6.2. Reals,
3.6.3. Strings,
3.7. Data Types,
3.7.1. Net Types,
Wire and Tri Nets,
Wor and Trior Nets,
Wand and Triand Nets,
Trireg Net,
Tri0 and Tri1 Nets,
Supply0 and Supply1 Nets,
3.7.2. Undeclared Nets,
3.7.3. Vectored and Scalared Nets,
3.7.4. Variable Types,
Reg Variable,
Memories,
Integer Variable,
Time Variable,
Real and Realtime Variable,
3.7.5. Arrays,
3.7.6. Difference between Reg and Wire,
3.8. Parameters,
3.8.1. Local Parameters,
3.9. Exercises, Chapter 4 Expressions
4.1. Operands,
4.1.1. Constant,
4.1.2. Parameter,
4.1.3. Net,
4.1.4. Variable,
4.1.5. Bit-select,
4.1.6. Part-select,
4.1.7. Memory and Array Element,
4.1.8. Function Call,
4.1.9. Signedness,
4.2. Operators,
4.2.1. Arithmetic Operators,
Result Size,
Unsigned and Signed,
4.2.2. Relational Operators,
4.2.3. Equality Operators,
4.2.4. Logical Operators,
4.2.5. Bit-wise Operators,
4.2.6. Reduction Operators,
4.2.7. Shift Operators,
4.2.8. Conditional Operator,
4.2.9. Concatenation and Replication,
4.3. Kinds of Expressions,
4.4. Exercises, Chapter 5 Gate-level Modeling
5.1. The Built-in Primitive Gates,
5.2. Multiple-input Gates,
5.3. Multiple-output Gates,
5.4. Tristate Gates,
5.5. Pull Gates,
5.6. MOS Switches,
5.7. Bidirectional Switches,
5.8. Gate Delays,
5.8.1. Min:typ:max Delay Form,
5.9. Array of Instances,
5.10. Implicit Nets,
5.11. A Simple Example,
5.12. A 2-to-4 Decoder Example,
5.13. A Master-slave Flip-flop Example,
5.14. A Parity Circuit,
5.15. Exercises, Chapter 6 User-Defined Primitives
6.1. Defining a UDP,
6.2. Combinational UDP,
6.3. Sequential UDP,
6.3.1. Initializing the State Variable,
6.3.2. Level-sensitive Sequential UDP,
6.3.3. Edge-triggered Sequential UDP,
6.3.4. Mixing Edge-triggered and Level-sensitive Behavior,
6.4. Another Example,
6.5. Summary of Table Entries,
6.6. Exercises, Chapter 7 Dataflow Modeling
7.1. Continuous Assignment,
7.2. An Example,
7.3. Net Declaration Assignment,
7.4. Delays,
7.5. Net Delays,
7.6. Examples,
7.6.1. Master-slave Flip-flop,
7.6.2. Magnitude Comparator,
7.7. Exercises, Chapter 8 Behavioral Modeling
8.1. Procedural Constructs,
8.1.1. Initial Statement,
8.1.2. Always Statement,
8.1.3. In One Module,
8.2. Timing Controls,
8.2.1. Delay Control,
8.2.2. Event Control,
Edge-triggered Event Control,
Level-sensitive Event Control,
8.3. Block Statement,
8.3.1. Sequential Block,
8.3.2. Parallel Block,
8.4. Procedural Assignments,
8.4.1. Intra-statement Delay,
8.4.2. Blocking Procedural Assignment,
8.4.3. Nonblocking Procedural Assignment,
8.4.4. Continuous Assignment vs Procedural Assignment,
8.5. Conditional Statement,
8.6. Case Statement,
8.6.1. Don’t-cares in Case,
8.7. Loop Statement,
8.7.1. Forever-loop Statement,
8.7.2. Repeat-loop Statement,
8.7.3. While-loop Statement,
8.7.4. For-loop Statement,
8.8. Procedural Continuous Assignment,
8.8.1. Assign - deassign,
8.8.2. Force - release,
8.9. A Handshake Example,
8.10. Exercises, Chapter 9 Structural Modeling
9.1. Module,
9.2. Ports,
9.2.1. Parameter Ports,
9.3. Module Instantiation,
9.3.1. Unconnected Ports,
9.3.2. Different Port Lengths,
9.3.3. Module Parameter Values,
Defparam Statement,
Module Instance Parameter Value Assignment,
9.4. External Ports,
9.5. Examples,
9.6. Generate Statement,
9.6.1. Generate-loop,
9.6.2. Generate-conditional,
9.6.3. Generate-case,
9.7. Configurations,
9.8. Exercises, Chapter 10 Other Topics
10.1. Tasks,
10.1.1. Task Definition,
10.1.2. Task Calling,
10.2. Functions,
10.2.1. Function Definition,
10.2.2. Function Call,
10.2.3. Constant Functions,
10.3. System Tasks and Functions,
10.3.1. Display Tasks,
Display and Write Tasks,
Strobe Tasks,
Monitor Tasks,
10.3.2. File I/O Tasks,
Opening and Closing Files,
Writing out to a File,
Reading from a File,
Annotating from a SDF file,
10.3.3. Timescale Tasks,
10.3.4. Simulation Control Tasks,
10.3.5. Simulation Time Functions,
10.3.6. Conversion Functions,
10.3.7. Probabilistic Distribution Functions,
10.3.8. String Formatting,
10.4. Disable Statement,
10.5. Named Events,
10.6. Mixing Structure with Behavior,
10.7. Hierarchical Path Name,
10.8. Sharing Tasks and Functions,
10.9. Attributes,
10.10. Value Change Dump (VCD) File,
10.10.1. Four-state VCD File,
10.10.2. Extended VCD File,
10.10.3. An Example,
10.10.4. Format of VCD File,
10.11. Specify Block,
10.12. Strengths,
10.12.1. Drive Strength,
10.12.2. Charge Strength,
10.13. Race Condition,
10.14. Command Line Arguments,
10.15. Exercises, Chapter 11 Verification
11.1. Writing a Test Bench,
11.2. Waveform Generation,
11.2.1. A Sequence of Values,
11.2.2. Repetitive Patterns,
11.3. Testbench Examples,
11.3.1. A Decoder,
11.3.2. A Flip-flop,
11.4. Reading Vectors from a Text File,
11.5. Writing Vectors to a Text File,
11.6. Some More Examples,
11.6.1. A Clock Divider,
11.6.2. A Factorial Design,
11.6.3. A Sequence Detector,
11.6.4. A LED Sequencer,
11.7. Utilities,
11.7.1. Checking for x,
11.7.2. Passing a File to a Task,
11.7.3. Debugging Opcodes,
11.7.4. Check No Missing Clock,
11.7.5. Clock Burst Generator,
11.8. Exercises, Chapter 12 Modeling Examples
12.1. Modeling Simple Elements,
12.2. Different Styles of Modeling,
12.3. Modeling Delays,
Transport Delays,
12.4. Modeling a Truth Table,
12.5. Modeling Conditional Operations,
12.6. Modeling Synchronous Logic,
12.7. A Generic Shift Register,
12.8. A Gray Counter,
12.9. A Decade Counter,
12.10. Parallel to Serial Converter,
12.11. State Machine Modeling,
12.12. Interacting State Machines,
12.13. Modeling a Moore FSM,
12.14. Modeling a Mealy FSM,
12.15. A Simplified Blackjack Program,
12.16. A Scan Cell,
12.17. A BCD to 7-segment Decoder,
12.18. Utilities,
12.18.1. Default Value on a Bus,
12.19. Exercises, Appendix A Syntax Reference
A.1. Keywords,
A.2. Syntax Conventions,
A.3. The Syntax, Bibliography Index
"About this title" may belong to another edition of this title.
- PublisherStar Galaxy Pub
- Publication date2005
- ISBN 10 0965039161
- ISBN 13 9780965039161
- BindingHardcover
- LanguageEnglish
- Edition number3
- Number of pages400
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