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Synopsis
Written for new users.
Explains the language through simple examples.
Explains the syntax of language using commonly-used design terminology.
Explains the behavioral style, the dataflow style, and structural style in detail.
Concepts of delay and timing are clearly explained.
Testbench writing is made easier by providing a number of examples.
Many hardware modeling examples have also been provided to make this an excellent reference.
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From the Back Cover
"A must primer for anyone who is beginning to learn Verilog HDL"
"An excellent reference book that shows many modeling examples"
Learn Verilog HDL the fast and easy way. Use this primer for a thorough understanding of the basic building blocks of Verilog HDL.
Find out how to model hardware and test it using the various constructs provided by Verilog HDL.
About the Author
J. Bhasker is a Distinguished Member of Technical Staff at Bell Laboratories at Lucent Technologies. He has taught VHDL and Verilog HDL courses at Lucent Technologies for more than four years. He has also authored four other books in hardware description languages and synthesis including the best-selling books "A VHDL Primer" and "A VHDL Synthesis Primer". Bhasker has a PhD in Computer Science from the University of Minnesota, M.Tech. in Computer Technology and a B.Tech. in Electrical Enginering from the Indian Institute of Technology, New Delhi.
"About this title" may belong to another edition of this title.
- PublisherStar Galaxy Press
- Publication date1997
- ISBN 10 0965627748
- ISBN 13 9780965627740
- BindingHardcover
- LanguageEnglish
- Number of pages259
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