Synopsis
This unique description of the Intel® Itanium™ application architecture helps the software development community to use the power of Intel's new line of 64-bit processors. The book provides:
- Knowledge that helps developers understand how to create high-performance software by tapping the unique features of the architecture and corresponding compilers.
- Clear explanation of how the massively parallel Itanium architecture meets demand for increased throughput by Internet-based applications and e-Commerce.
- Highlights of unique concepts that help the reader to understand how the new architecture differs from traditional IA-32 architectures.
- Descriptions of salient features of the Itanium™ processor's application software architecture.
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About the Author
Walter Triebel is the author of 17 books on microprocessors, digital logic, and memory. His most recent title is Itanium® Architecture for Software Developers. Along with enthusiasm for the technology, he brings to the book over twenty years of experience as an application engineer and educator. He has worked seventeen years for Intel Corporation, currently as a writer-in-residence for Intel Press. He holds a Bachelor of Science in Electrical Engineering from Fairleigh Dickinson University and a Master of Science Degree in Electrical Engineering from New York University.
Excerpt. © Reprinted by permission. All rights reserved.
The faster you make a computer run, the harder it is to envision how to make it run still faster. It is no longer sufficient to just make the architecture process instructions faster. You must make more things happen at once that is, in parallel. The computer is not running faster it is simply getting more done at once.
The Itanium architecture employs a new parallel computer architecture called explicitly parallel instruction computing (EPIC). Intel Corporation s first hardware implementation of this architecture is the Itanium processor. EPIC offers many new features to increase performance, but the most important are explicit instruction level parallelism (ILP), speculation, predication, and a large register file. Each of these makes a computer run faster.
But what do you do with all this parallelism? The traditional problem is that we never have enough work ready to keep a machine fully busy. If we have all this power, the key is to not throw it away by letting it go unused. Anytime the processor is ready to do six more things, we don t want to give it two things to do and waste 66% of the processing power. A breakthrough happens when you decide to stop worrying about only doing things we must. The approach is to ask the machine speculatively to do four more things. That is, things are picked that might be needed in the future, but right now we just aren t sure which of the four it will be. Let us say that the four extra things turn out to be needed only half the time. We are still better off than if we had asked the processor to do nothing. Half of the time the work is done by the time it is needed.In fact, this is the promise of explicitly parallel instruction computing. As machines get wider and wider, we just speculate more and more. The goal is to compute results before they are needed, so that when a program needs them, the answers are already there. Nothing is faster than something that is already done!
In a traditional microprocessor, doing things in advance can create trouble. For instance, if AB is computed too early, the values of A or B might change and make the original result useless. The sum of A and B must be recomputed. Because of these problems, the architecture requires special features for speculation that make these exceptions efficient to detect and correct. Speculation is a big part of what EPIC offers, and it is offered in many forms. But, all the speculation features are simply in EPIC to allow us to compute things before they are needed, and before a check is made to ensure that it is not too early to do the work.
EPIC builds on the abilities of a very long instruction word (VLIW) machine by allowing the selection of instructions to be executed in parallel to be done at compile time. For this reason, compilers may be the most important component of EPIC. Compilers to harness the instruction level parallelism are very complex. EPIC architecture is optimized for compiler writers, to simplify the task of writing the advanced compilers needed for EPIC. The goal of Itanium architectural features, such as speculation, predication, and a large register file, is to simplify the problems that a compiler writer faces so that it is possible to write good compilers to use EPIC. The first thing EPIC offers to compilers is explicit access to the parallelism hence the term EPIC. This access is a bonus for the compiler writer and the microprocessor designer. Both jobs are simplified by opening up the communication between compiled code and the hardware. Once explicit parallelism is available, the challenge is to make full use of it. Speculative execution of instructions is the most important concept in EPIC for helping a compiler fill up the available parallelism. It is what makes it possible to believe that programs can be written to use the parallelism available. More importantly, speculative execution allows compiler writers to compile programs into parallel code for the processor.
Predication is the second most important concept in EPIC for filling up the available parallelism. Practically every instruction that is executed is conditional, based on a predicate register. Each instruction either has an effect, or has no effect, based on the True or False condition in a predicate register. Branches in program control impede full use of parallelism. This predication of every instruction, with no extra run-time cost, allows the elimination of a branch, thereby increasing parallelism.
EPIC also offers very large register sets. Asmaller register set limits performance. The processor has to shuffle data in and out of registers instead of doing the work required for the program. The registers in the Itanium architecture even offer a feature called rotating registers, which reduces the need for register shuffling and code duplication when doing a type of loop level parallelism called software pipelining. Finally, EPIC acknowledges that the parallelism, which a compiler can find, is not consistent from clock to clock, and machine width is not fixed for every microprocessor design. The Itanium processor is six execution units wide, but cannot do every combination of six things at once. Therefore, EPIC allows code to express where the parallelism is, without forcing all code to be six wide forever. Future Itanium processors may be more flexible about what they can do in parallel or how many things can be done in parallel, or both. In earlier VLIW machines, inflexibility was a substantial problem in their designs. Width changed from generation to generation of the machine and the code compiled for one machine did not work on another. That is, they were not scalable. EPIC solves the scalability problem and code can execute across all Itanium-based computers.
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