Synopsis
* Demonstrates by example how to write requirement specs, implementation plan, verification plan, documentation.
* Demonstrates design and verification issues and reusable parser package
* Saves $$ thru proper planning of a design
EE Times January 8, 20001 Article on "Book Models ASIC Design Process"
"synopsis" may belong to another edition of this title.
About the Author
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
"About this title" may belong to another edition of this title.
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