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Synopsis
This book addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices expressed with Verilog and VHDL. Topics: 1. Architectural decomposition process; 2. Fundamental elements including synchronous edge detector, counter styles (e.g., Binary, One-Hot, Gray, Johnson), memories (ROM. RAM, FIFO), EDAC, cell primitives and impact on architecture, clocking schemes and PLL; 3. Asynchronous world, metastability, asynchronous FIFO, crossing clock domains; 4. Transaction-based verification methodology, forcing errors, counter and EDAC verification models; 5. Control machines and implementation methodologies with FSM and microprogrammed solutions; 6. Arithmetic machines, HDL Signed and Unsigned types; 7. Mixed mode simulations and synthesis; 8. Minimizing design errors; 9. Verilog/VHDL comparison, Verilog for VHDL users, Verilog coding style guidelines.
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About the Author
Ben Cohen authored the following books:
VHDL Coding Styles and Methodologies,
first and second editions,
VHDL Answers to Frequently Asked Questions, first and second editions
Component Design by Example
... a Step-by-Step Process Using VHDL with UART as Vehicle
"About this title" may belong to another edition of this title.
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Real Chip Design and Verification Using Verilog and VHDL
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