The Art of Verification with SystemVerilog Assertions - Softcover

Faisal Haque; Jonathan Michelson; Khizar Khan

Softcover

ISBN 10: 0971199418 ISBN 13: 9780971199415

Publisher: Verification Central, 2006

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The Art of Verification with SystemVerilog Assertions (SVA) covers all aspects of SVA with numerous, detailed examples. The book demonstrates how SVA can be harnessed to implement effective, assertion-based verification.

It teaches the SVA language by explaining its usage in the context of practical verification issues. SVA syntax and features are explained in simple and easy-to-understand language. The usage of each construct is illustrated with both simple examples and examples...

About the Author

Faisal Haque has 20+ years experience in high-level verification and design of complex networking hardware. He was the former chair of SystemVerilog Assertions committee and is currently chairing the UCIS committee. He received his bachelors in electrical engineering from the University of Notre Dame.

Jonathan Michelson has 12+ years of experience designing and verifying complex designs. He was co-designer of a verification language and methodology at Silicon Graphics....

Review

"The simple examples taught me the fundamental concepts of SVA while the real life examples solidified my understanding of the language and helped me apply it to my own verification challenges. Once again, the authors clearly explain complex verification subjects and by doing so address a need in the chip development community." --Vincent Au, Verification Engineer, Ambarella Corporation

"Verification Central has provided an invaluable resource for design and verification engineers. The...

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