Items related to Logic Design and Verification Using SystemVerilog (Revised)
Synopsis
SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: •students currently in an introductory logic design course that also teaches SystemVerilog, •designers who...
About the Author
Donald Thomas is Professor Emeritus of Electrical and Computer Engineering at Carnegie Mellon University where he has taught logic design, RT-level design, design languages (Verilog and SystemVerilog), verification, and computer-aided design algorithms for the design of integrated circuits and systems.
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- PublisherCreateSpace Independent Publishing Platform
- Publication date2016
- ISBN 10 1523364025
- ISBN 13 9781523364022
- BindingPaperback
- LanguageEnglish
- Number of pages336
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Logic Design and Verification Using SystemVerilog (Revised)
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Logic Design and Verification Using SystemVerilog (Revised)
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Logic Design and Verification Using SystemVerilog (Revised)
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CreateSpace Independent Publishing Platform (edition Revised), 2016
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Logic Design and Verification Using Systemverilog
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Logic Design and Verification Using SystemVerilog (Revised)
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Logic Design and Verification Using SystemVerilog (Revised)
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Logic Design and Verification Using SystemVerilog (Revised)
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Logic Design and Verification Using Systemverilog
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ISBN 13: 9781523364022
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Logic Design and Verification Using Systemverilog
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Logic Design and Verification Using Systemverilog
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ISBN 10: 1523364025
ISBN 13: 9781523364022
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Seller: GreatBookPricesUK, Woodford Green, United Kingdom
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