Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits - Softcover
Synopsis
The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops.
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About the Author
Dr. Hassan Mostafa received his PhD in Electrical and Computer Engineering from the University of Waterloo, Canada in 2011. Dr. Mostafa has worked as a research associate with Fujitsu labs (Japan), University of Toronto, Canada, and IMEC (Belgium). He has authored/coauthored over 35 papers in international journals and conferences.
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Design for Yield and Reliability for Nanometer CMOS Digital Circuits
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. 296 pp. Englisch. Seller Inventory # 9783659513619
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Design for Yield and Reliability for Nanometer CMOS Digital Circuits
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Design for Yield and Reliability for Nanometer CMOS Digital Circuits
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Mostafa HassanDr. Hassan Mostafa received his PhD in Electrical and Computer Engineering from the University of Waterloo, Canada in 2011. Dr. Mostafa has worked as a research associate with Fujitsu labs (Japan), University of Toronto. Seller Inventory # 5161463
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Design for Yield and Reliability for Nanometer CMOS Digital Circuits
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Design for Yield and Reliability for Nanometer CMOS Digital Circuits
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Design for Yield and Reliability for Nanometer CMOS Digital Circuits
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Taschenbuch. Condition: Neu. Neuware -The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops.Books on Demand GmbH, Überseering 33, 22297 Hamburg 296 pp. Englisch. Seller Inventory # 9783659513619
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Design for Yield and Reliability for Nanometer CMOS Digital Circuits | Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits
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Taschenbuch. Condition: Neu. Design for Yield and Reliability for Nanometer CMOS Digital Circuits | Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits | Hassan Mostafa (u. a.) | Taschenbuch | 296 S. | Englisch | 2014 | LAP LAMBERT Academic Publishing | EAN 9783659513619 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu. Seller Inventory # 105471775
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Design for Yield and Reliability for Nanometer CMOS Digital Circuits : Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits
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ISBN 13: 9783659513619
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Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits
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