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PVT Variation Aware Low Power Vedic Multiplier Design For DSPs on FPGA: Process Voltage Temperature Variation Using IO Standards on FPGA - Softcover
Synopsis
As the communication and signal processing industries are proliferating the demand for the multipliers is continuously increasing at a rapid rate. For researchers, to develop high speed and power efficient multiplier has been a grave matter of concern. Reduction in the power consumption and delay of a multiplier circuitry is expected to cause a revolution in the field of electronics and communication.The performance of system is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Hence, optimizing the speed and power consumption of the multiplier is a major design issue. There is need of development of high speed and low power multiplier for digital signal processing algorithms. From the previous research, it has been concluded that Vedic multiplier are more efficient than conventional multiplier. In this work, low power Vedic multiplier has been proposed.
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About the Author
Kavita Goswami has authored and co-authored many papers in international IEEE conference & Scopus Index Journal in area of low power VLSI design. She has received B.Tech. in ECE from Kurukshetra University. Currently she is pursuing ME in ECE from Chitkara University. She has 2+ year experience in teaching of digital and analog IC design and FPGA.
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- PublisherLAP LAMBERT Academic Publishing
- Publication date2014
- ISBN 10 3659629359
- ISBN 13 9783659629358
- BindingPaperback
- LanguageEnglish
- Number of pages104
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PVT Variation Aware Low Power Vedic Multiplier Design For DSPs on FPGA
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LAP LAMBERT Academic Publishing Nov 2014, 2014
ISBN 10: 3659629359
ISBN 13: 9783659629358
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -As the communication and signal processing industries are proliferating the demand for the multipliers is continuously increasing at a rapid rate. For researchers, to develop high speed and power efficient multiplier has been a grave matter of concern. Reduction in the power consumption and delay of a multiplier circuitry is expected to cause a revolution in the field of electronics and communication.The performance of system is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Hence, optimizing the speed and power consumption of the multiplier is a major design issue. There is need of development of high speed and low power multiplier for digital signal processing algorithms. From the previous research, it has been concluded that Vedic multiplier are more efficient than conventional multiplier. In this work, low power Vedic multiplier has been proposed. 104 pp. Englisch. Seller Inventory # 9783659629358
Quantity: 2 available
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PVT Variation Aware Low Power Vedic Multiplier Design For DSPs on FPGA : Process Voltage Temperature Variation Using IO Standards on FPGA
Published by
LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659629359
ISBN 13: 9783659629358
New
Taschenbuch
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - As the communication and signal processing industries are proliferating the demand for the multipliers is continuously increasing at a rapid rate. For researchers, to develop high speed and power efficient multiplier has been a grave matter of concern. Reduction in the power consumption and delay of a multiplier circuitry is expected to cause a revolution in the field of electronics and communication.The performance of system is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Hence, optimizing the speed and power consumption of the multiplier is a major design issue. There is need of development of high speed and low power multiplier for digital signal processing algorithms. From the previous research, it has been concluded that Vedic multiplier are more efficient than conventional multiplier. In this work, low power Vedic multiplier has been proposed. Seller Inventory # 9783659629358
Quantity: 1 available
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PVT Variation Aware Low Power Vedic Multiplier Design For DSPs on FPGA
Published by
LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659629359
ISBN 13: 9783659629358
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Softcover
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Goswami KavitaKavita Goswami has authored and co-authored many papers in international IEEE conference & Scopus Index Journal in area of low power VLSI design. She has received B.Tech. in ECE from Kurukshetra University. Currently sh. Seller Inventory # 5169553
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PVT Variation Aware Low Power Vedic Multiplier Design For DSPs on FPGA: Process Voltage Temperature Variation Using IO Standards on FPGA
Published by
LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659629359
ISBN 13: 9783659629358
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