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Synopsis
A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional.
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Design of Magnitude Comparator Using Reversible Logic Gates
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LAP LAMBERT Academic Publishing Sep 2018, 2018
ISBN 10: 3659796069
ISBN 13: 9783659796067
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional. 60 pp. Englisch. Seller Inventory # 9783659796067
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Design of Magnitude Comparator Using Reversible Logic Gates
Published by
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 3659796069
ISBN 13: 9783659796067
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Seller: AHA-BUCH GmbH, Einbeck, Germany
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional. Seller Inventory # 9783659796067
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Design of Magnitude Comparator Using Reversible Logic Gates
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Karunamurthi SaranyaK. Saranya, is a Assistant Professor, Department of EEE in Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu. India. She completed her M.E in department of Applied Electronics at Government . Seller Inventory # 385769389
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Design of Magnitude Comparator Using Reversible Logic Gates
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ISBN 13: 9783659796067
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Paperback. Condition: Brand New. 60 pages. 8.66x5.91x0.14 inches. In Stock. Seller Inventory # 3659796069
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Design of Magnitude Comparator Using Reversible Logic Gates
Published by
LAP LAMBERT Academic Publishing Sep 2018, 2018
ISBN 10: 3659796069
ISBN 13: 9783659796067
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 60 pp. Englisch. Seller Inventory # 9783659796067
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Design of Magnitude Comparator Using Reversible Logic Gates
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ISBN 10: 3659796069
ISBN 13: 9783659796067
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Taschenbuch. Condition: Neu. Design of Magnitude Comparator Using Reversible Logic Gates | Saranya Karunamurthi (u. a.) | Taschenbuch | 60 S. | Englisch | 2018 | LAP LAMBERT Academic Publishing | EAN 9783659796067 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 114718798
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Design of Magnitude Comparator Using Reversible Logic Gates
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ISBN 10: 3659796069
ISBN 13: 9783659796067
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