Synopsis
The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence, performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application. The proposed technique is expected to enhance the performance of the NoC.
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About the Author
Muhamad Qaedi Edanan is a Bachelor in Electronic Engineering (Computer) from Universiti Malaysia Sarawak (UNIMAS). Asrani Lit is a Research Scientist at Department of Electrical and Electronic in UNIMAS.
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Performance Optimization in Network-on-Chip
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LAP LAMBERT Academic Publishing Jun 2016, 2016
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence, performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application. The proposed technique is expected to enhance the performance of the NoC. 80 pp. Englisch. Seller Inventory # 9783659907456
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Performance Optimization in Network-on-Chip: Multi Level Network Partitioning Approach
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Lit AsraniMuhamad Qaedi Edanan is a Bachelor in Electronic Engineering (Computer) from Universiti Malaysia Sarawak (UNIMAS). Asrani Lit is a Research Scientist at Department of Electrical and Electronic in UNIMAS.The increasing c. Seller Inventory # 385770553
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Performance Optimization in Network-on-Chip
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LAP LAMBERT Academic Publishing Jun 2016, 2016
ISBN 10: 3659907456
ISBN 13: 9783659907456
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Taschenbuch. Condition: Neu. Neuware -The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence, performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application. The proposed technique is expected to enhance the performance of the NoC.Books on Demand GmbH, Überseering 33, 22297 Hamburg 80 pp. Englisch. Seller Inventory # 9783659907456
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Performance Optimization in Network-on-Chip : Multi Level Network Partitioning Approach
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LAP LAMBERT Academic Publishing, 2016
ISBN 10: 3659907456
ISBN 13: 9783659907456
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence, performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application. The proposed technique is expected to enhance the performance of the NoC. Seller Inventory # 9783659907456