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Analysis and Design of a DRAM Cell for Low Leakage: Process Level Techniques for Leakage Reduction - Softcover
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In Dynamic Random Access Memory, every cell experiences leakage current which consumes part of the stored charge. As the DRAM cell size is shrinking, the leakage is increasing. To maintain the desired data retention time, the leakage current must be kept within the acceptable limit. So, leakage reduction in memories is a topic of great challenge and interest in researchers. This book presents the analysis and design of a DRAM cell for low leakage. For the analysis, trench capacitor DRAM cell has been considered. For the design of trench capacitor DRAM cell, 0.18 ?m submicron nMOSFET as access transistor and the conventional trench capacitor as storage device have been considered. Various DRAM cell structures, leakage mechanisms in a DRAM cell and process-level techniques for leakage reduction have been reviewed. Process simulation and device simulation of DRAM cell have been done using the ATHENA/ATLAS packages of SILVACO. This book will help the beginners as the book reviews the previous work done by many researchers and provides the trends in DRAM cell designs, theoretical knowledge of leakage mechanisms in DRAM cell and process/device simulation of DRAM cell.
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Analysis and Design of a DRAM Cell for Low Leakage
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LAP LAMBERT Academic Publishing Jan 2010, 2010
ISBN 10: 3838339436
ISBN 13: 9783838339436
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In Dynamic Random Access Memory, every cell experiences leakage current which consumes part of the stored charge. As the DRAM cell size is shrinking, the leakage is increasing. To maintain the desired data retention time, the leakage current must be kept within the acceptable limit. So, leakage reduction in memories is a topic of great challenge and interest in researchers. This book presents the analysis and design of a DRAM cell for low leakage. For the analysis, trench capacitor DRAM cell has been considered. For the design of trench capacitor DRAM cell, 0.18 m submicron nMOSFET as access transistor and the conventional trench capacitor as storage device have been considered. Various DRAM cell structures, leakage mechanisms in a DRAM cell and process-level techniques for leakage reduction have been reviewed. Process simulation and device simulation of DRAM cell have been done using the ATHENA/ATLAS packages of SILVACO. This book will help the beginners as the book reviews the previous work done by many researchers and provides the trends in DRAM cell designs, theoretical knowledge of leakage mechanisms in DRAM cell and process/device simulation of DRAM cell. 56 pp. Englisch. Seller Inventory # 9783838339436
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Analysis and Design of a DRAM Cell for Low Leakage
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ISBN 10: 3838339436
ISBN 13: 9783838339436
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. In Dynamic Random Access Memory, every cell experiences leakage current which consumes part of the stored charge. As the DRAM cell size is shrinking, the leakage is increasing. To maintain the desired data retention time, the leakage current must be kept wi. Seller Inventory # 5414469
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Analysis and Design of a DRAM Cell for Low Leakage : Process Level Techniques for Leakage Reduction
Published by
LAP LAMBERT Academic Publishing, 2010
ISBN 10: 3838339436
ISBN 13: 9783838339436
New
Taschenbuch
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In Dynamic Random Access Memory, every cell experiences leakage current which consumes part of the stored charge. As the DRAM cell size is shrinking, the leakage is increasing. To maintain the desired data retention time, the leakage current must be kept within the acceptable limit. So, leakage reduction in memories is a topic of great challenge and interest in researchers. This book presents the analysis and design of a DRAM cell for low leakage. For the analysis, trench capacitor DRAM cell has been considered. For the design of trench capacitor DRAM cell, 0.18 m submicron nMOSFET as access transistor and the conventional trench capacitor as storage device have been considered. Various DRAM cell structures, leakage mechanisms in a DRAM cell and process-level techniques for leakage reduction have been reviewed. Process simulation and device simulation of DRAM cell have been done using the ATHENA/ATLAS packages of SILVACO. This book will help the beginners as the book reviews the previous work done by many researchers and provides the trends in DRAM cell designs, theoretical knowledge of leakage mechanisms in DRAM cell and process/device simulation of DRAM cell. Seller Inventory # 9783838339436
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Analysis and Design of a DRAM Cell for Low Leakage
Published by
LAP LAMBERT Academic Publishing Jan 2010, 2010
ISBN 10: 3838339436
ISBN 13: 9783838339436
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Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In Dynamic Random Access Memory, every cell experiences leakage current which consumes part of the stored charge. As the DRAM cell size is shrinking, the leakage is increasing. To maintain the desired data retention time, the leakage current must be kept within the acceptable limit. So, leakage reduction in memories is a topic of great challenge and interest in researchers. This book presents the analysis and design of a DRAM cell for low leakage. For the analysis, trench capacitor DRAM cell has been considered. For the design of trench capacitor DRAM cell, 0.18 ¿m submicron nMOSFET as access transistor and the conventional trench capacitor as storage device have been considered. Various DRAM cell structures, leakage mechanisms in a DRAM cell and process-level techniques for leakage reduction have been reviewed. Process simulation and device simulation of DRAM cell have been done using the ATHENA/ATLAS packages of SILVACO. This book will help the beginners as the book reviews the previous work done by many researchers and provides the trends in DRAM cell designs, theoretical knowledge of leakage mechanisms in DRAM cell and process/device simulation of DRAM cell.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Englisch. Seller Inventory # 9783838339436
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Analysis and Design of a DRAM Cell for Low Leakage: Process Level Techniques for Leakage Reduction
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ISBN 10: 3838339436
ISBN 13: 9783838339436
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