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ASIC Design for a Coherent Optical Receiver DSPU: Design issues related to high-speed MOS ASIC for a coherent optical QPSK with polarization multiplex receiver DSPU - Softcover
Synopsis
The exponential growth of the internet traffic makes it necessary to increase the transmission capacity of the backbone optical transmission system. The coherent optical quadrature PSK (QPSK) with polarization multiplex quadruple channel capacity over the intensity modulation scheme. This upgrades existing 10 Gbit/s links to 40 Gbit/s. This book introduces you to the practicle implementation of the receiver DSPU ASIC of such a system. Chapter 1 introduces the design problem. Chapter 2 starts with an introduction to the optical synchronous QPSK transmission systems and discusses the carrier & data recovery algorithms. Chapter 2 concludes with an introduction to the DSPU ASIC architecture. Chapter 3 discusses the implementation of the DSPU ASIC. The chapter starts with an introduction to the 130 nm technology node and then discuss transmission line implementation issues, DSPU input interface design, and the full DSPU implementation. Finally, test results are presented. Chapter 4 introduces a novel clock skew estimation algorithm. This algorithm calculates the clock skew when process variations and nonuniform temparature varitions are present.
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About the Author
Dr. Vijitha R. Herath received BS(EE)from the University of Peradeniya, Sri Lanka, MS(ECE) from the University of Miami, USA, and Dr. -Ing. (EE) from the University of Paderborn, Germany. He is a member of IEEE, OSA and IEEE MTT-S Sri Lanka chapter. He is attached to the Dept. of Electrical & Electronic Eng., University of Peradeniya.
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ASIC Design for a Coherent Optical Receiver DSPU
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LAP LAMBERT Academic Publishing Feb 2011, 2011
ISBN 10: 3844304193
ISBN 13: 9783844304190
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The exponential growth of the internet traffic makes it necessary to increase the transmission capacity of the backbone optical transmission system. The coherent optical quadrature PSK (QPSK) with polarization multiplex quadruple channel capacity over the intensity modulation scheme. This upgrades existing 10 Gbit/s links to 40 Gbit/s. This book introduces you to the practicle implementation of the receiver DSPU ASIC of such a system. Chapter 1 introduces the design problem. Chapter 2 starts with an introduction to the optical synchronous QPSK transmission systems and discusses the carrier & data recovery algorithms. Chapter 2 concludes with an introduction to the DSPU ASIC architecture. Chapter 3 discusses the implementation of the DSPU ASIC. The chapter starts with an introduction to the 130 nm technology node and then discuss transmission line implementation issues, DSPU input interface design, and the full DSPU implementation. Finally, test results are presented. Chapter 4 introduces a novel clock skew estimation algorithm. This algorithm calculates the clock skew when process variations and nonuniform temparature varitions are present. 112 pp. Englisch. Seller Inventory # 9783844304190
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ASIC Design for a Coherent Optical Receiver DSPU
Published by
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3844304193
ISBN 13: 9783844304190
New
Softcover
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Herath Vijitha RohanaDr. Vijitha R. Herath received BS(EE)from the University of Peradeniya, Sri Lanka, MS(ECE) from the University of Miami, USA, and Dr. -Ing. (EE) from the University of Paderborn, Germany. He is a member of IEE. Seller Inventory # 5470916
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ASIC Design for a Coherent Optical Receiver DSPU
Published by
LAP LAMBERT Academic Publishing Feb 2011, 2011
ISBN 10: 3844304193
ISBN 13: 9783844304190
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. Neuware -The exponential growth of the internet traffic makes it necessary to increase the transmission capacity of the backbone optical transmission system. The coherent optical quadrature PSK (QPSK) with polarization multiplex quadruple channel capacity over the intensity modulation scheme. This upgrades existing 10 Gbit/s links to 40 Gbit/s. This book introduces you to the practicle implementation of the receiver DSPU ASIC of such a system. Chapter 1 introduces the design problem. Chapter 2 starts with an introduction to the optical synchronous QPSK transmission systems and discusses the carrier & data recovery algorithms. Chapter 2 concludes with an introduction to the DSPU ASIC architecture. Chapter 3 discusses the implementation of the DSPU ASIC. The chapter starts with an introduction to the 130 nm technology node and then discuss transmission line implementation issues, DSPU input interface design, and the full DSPU implementation. Finally, test results are presented. Chapter 4 introduces a novel clock skew estimation algorithm. This algorithm calculates the clock skew when process variations and nonuniform temparature varitions are present.Books on Demand GmbH, Überseering 33, 22297 Hamburg 112 pp. Englisch. Seller Inventory # 9783844304190
Quantity: 2 available
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ASIC Design for a Coherent Optical Receiver DSPU : Design issues related to high-speed MOS ASIC for a coherent optical QPSK with polarization multiplex receiver DSPU
Published by
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3844304193
ISBN 13: 9783844304190
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The exponential growth of the internet traffic makes it necessary to increase the transmission capacity of the backbone optical transmission system. The coherent optical quadrature PSK (QPSK) with polarization multiplex quadruple channel capacity over the intensity modulation scheme. This upgrades existing 10 Gbit/s links to 40 Gbit/s. This book introduces you to the practicle implementation of the receiver DSPU ASIC of such a system. Chapter 1 introduces the design problem. Chapter 2 starts with an introduction to the optical synchronous QPSK transmission systems and discusses the carrier & data recovery algorithms. Chapter 2 concludes with an introduction to the DSPU ASIC architecture. Chapter 3 discusses the implementation of the DSPU ASIC. The chapter starts with an introduction to the 130 nm technology node and then discuss transmission line implementation issues, DSPU input interface design, and the full DSPU implementation. Finally, test results are presented. Chapter 4 introduces a novel clock skew estimation algorithm. This algorithm calculates the clock skew when process variations and nonuniform temparature varitions are present. Seller Inventory # 9783844304190
Quantity: 1 available
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ASIC Design for a Coherent Optical Receiver DSPU: Design issues related to high-speed MOS ASIC for a coherent optical QPSK with polarization multiplex receiver DSPU
Published by
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3844304193
ISBN 13: 9783844304190
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