Timing and Signal Integrity Issues with VLSI Interconnects: In sub-nanometer designs - Softcover

Das, Debaprasad

Softcover

ISBN 10: 3846552437 ISBN 13: 9783846552438

Publisher: LAP LAMBERT Academic Publishing, 2011

Synopsis

This book discusses the timing and signal integrity issues with VLSI interconnects in sub-nanometer designs. Starting with the basics of interconnect equivalent circuit model it describes the RLC equivalent models of interconnects, their extraction methodologies, and circuit simulation for timing and signal integrity analysis. With enormous analysis results for different technology nodes the importance of on-chip inductive effects has been discussed. The sample simulation model along with the SPICE netlist for timing and signal integrity analysis has been provided in the appendix. The book will be useful to the teachers, students, and researchers who are involved in modeling and analyzing the interconnects in future generation VLSI technology nodes. The book comprises four chapters and one appendix.

About this title

About the Author

Debaprasad Das is Assistant Professor, Department of Electronics and Communication Engineering, Meghnad Saha Institute of Technology, Kolkata, India. He was a Senior Engineer at the ASIC product development centre, Texas Instruments, Bangalore, India. He has published many national and international papers in various conferences and journals.

Edition details

• Publisher: LAP LAMBERT Academic Publishing
• Publication date: 2011
• Language: English
• ISBN 10: 3846552437
• ISBN 13: 9783846552438
• Binding: Paperback
• Number of pages: 84