Performance & Power Impact of Multiple DRAM Address Mapping Schemes: The Performance and Power Impact of Using Multiple DRAM Address Mapping Schemes in Multicore Processors - Softcover

Jadaa, Rami

Softcover

ISBN 10: 3847376217 ISBN 13: 9783847376217

Publisher: LAP LAMBERT Academic Publishing, 2012

Synopsis

Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of...

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About the Author

Rami received the Bachelor's degree in Electrical Engineering from the University of Sharjah, U.A.E in 2006. He then was an engineer building scalable search systems for three years. In 2011, he earned the Masters Degree in Electrical Engineering from the University of Central Florida. He is currently with NVIDIA

Edition details

• Publisher: LAP LAMBERT Academic Publishing
• Publication date: 2012
• ISBN 10: 3847376217
• ISBN 13: 9783847376217
• Binding: Paperback
• Language: English
• Number of pages: 80