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Efficient Test Data Compression and Fault Analysis in VLSI Circuits: Test Data Compression and Decompression Using Efficient Bitmask and Dictionary Selection Method - Softcover
Synopsis
In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory. To test the particular circuit that time we will decompress the stored memory test data and then decompressed test data given to the Design Under Test (DUT). Finally DUT fault is tested and identified. It proposes a test compression technique using efficient dictionary selection and bitmask method to significantly reduce the testing time and memory requirements. This algorithm giving a best possible test compression of 92% when compared with other compression methods.
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits
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Scholars' Press Mai 2019, 2019
ISBN 10: 6138834305
ISBN 13: 9786138834304
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory. To test the particular circuit that time we will decompress the stored memory test data and then decompressed test data given to the Design Under Test (DUT). Finally DUT fault is tested and identified. It proposes a test compression technique using efficient dictionary selection and bitmask method to significantly reduce the testing time and memory requirements. This algorithm giving a best possible test compression of 92% when compared with other compression methods. 84 pp. Englisch. Seller Inventory # 9786138834304
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits: Test Data Compression and Decompression Using Efficient Bitmask and Dictionary Selection Method
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits: Test Data Compression and Decompression Using Efficient Bitmask and Dictionary Selection Method
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits : Test Data Compression and Decompression Using Efficient Bitmask and Dictionary Selection Method
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory. To test the particular circuit that time we will decompress the stored memory test data and then decompressed test data given to the Design Under Test (DUT). Finally DUT fault is tested and identified. It proposes a test compression technique using efficient dictionary selection and bitmask method to significantly reduce the testing time and memory requirements. This algorithm giving a best possible test compression of 92% when compared with other compression methods. Seller Inventory # 9786138834304
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Subramaniam SivaganesanSivaganesan S Received B.E in Electronics and Communication Engineering from VSB Engineering College, Karur and M.E in VLSI Design from Karpagam College of Engineering, Coimbatore, Presently Working as Assistan. Seller Inventory # 298499690
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits: Test Data Compression and Decompression Using Efficient Bitmask and Dictionary Selection Method
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits
Published by
Scholars' Press Mai 2019, 2019
ISBN 10: 6138834305
ISBN 13: 9786138834304
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Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory. To test the particular circuit that time we will decompress the stored memory test data and then decompressed test data given to the Design Under Test (DUT). Finally DUT fault is tested and identified. It proposes a test compression technique using efficient dictionary selection and bitmask method to significantly reduce the testing time and memory requirements. This algorithm giving a best possible test compression of 92% when compared with other compression methods.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 84 pp. Englisch. Seller Inventory # 9786138834304
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits | Test Data Compression and Decompression Using Efficient Bitmask and Dictionary Selection Method
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Taschenbuch. Condition: Neu. Efficient Test Data Compression and Fault Analysis in VLSI Circuits | Test Data Compression and Decompression Using Efficient Bitmask and Dictionary Selection Method | Sivaganesan Subramaniam | Taschenbuch | 84 S. | Englisch | 2019 | Scholars' Press | EAN 9786138834304 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 116832758
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits: Test Data Compression and Decompression Using Efficient Bitmask and Dictionary Selection Method
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